ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PFigure 22-8.SDA fromMaster AArbitration Between Two MastersSTARTMaster A LosesArbitration, SDA ASDASDA fromMaster BSDA LineSynchronizedSCL LineNote that arbitration is not allowed between:• A REPEATED START condition and a data bit.• A STOP condition and a data bit.• A REPEATED START and a STOP condition.It is the user software’s responsibility to ensure that these illegal arbitration conditions neveroccur. This implies that in multi-master systems, all data transfers must use the same compositionof SLA+R/W and data packets. In other words: All transmissions must contain the samenumber of data packets, otherwise the result of the arbitration is undefined.8271D–AVR–05/11222