ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/P9. System Clock and Clock Options9.1 Clock Systems and their DistributionFigure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocksneed not be active at a given time. In order to reduce power consumption, the clocks to modulesnot being used can be halted by using different sleep modes, as described in ”Power Managementand Sleep Modes” on page 40. The clock systems are detailed below.Figure 9-1.Clock DistributionAsynchronousTimer/CounterGeneral I/OModulesADCCPU CoreRAMFlash andEEPROMclk ADCclk I/OAVR ClockControl Unitclk CPUclk ASYclk FLASHSystem ClockPrescalerReset LogicWatchdog TimerSource clockWatchdog clockClockMultiplexerWatchdogOscillatorTimer/CounterOscillatorExternal ClockCrystalOscillatorLow-frequencyCrystal OscillatorCalibrated RCOscillator9.1.1 CPU Clock – clk CPUThe CPU clock is routed to parts of the system concerned with operation of the AVR core.Examples of such modules are the General Purpose Register File, the Status Register and thedata memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performinggeneral operations and calculations.9.1.2 I/O Clock – clk I/OThe I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.The I/O clock is also used by the External Interrupt module, but note that start condition detectionin the USI module is carried out asynchronously when clk I/O is halted, TWI addressrecognition in all sleep modes.Note:Note that if a level triggered interrupt is used for wake-up from Power-down, the required levelmust be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If thelevel disappears before the end of the Start-up Time, the MCU will still wake up, but no interruptwill be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in”System Clock and Clock Options” on page 27.8271D–AVR–05/1127