ATMega chip full datasheet - UCSD Department of Physics

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ATmega48A/PA/88A/PA/168A/PA/328/PFigure 29-3.SPI Interface Timing Requirements (Master Mode)SS6 1SCK(CPOL = 0)2 2SCK(CPOL = 1)4 53MISO(Data Input)MSB7...LSB8MOSI(Data Output)MSB...LSBFigure 29-4.SPI Interface Timing Requirements (Slave Mode)SS91016SCK(CPOL = 0)11 11SCK(CPOL = 1)13 1412MOSI(Data Input)MSB15...LSB17MISO(Data Output)MSB...LSBX8271D–AVR–05/11326
ATmega48A/PA/88A/PA/168A/PA/328/P29.7 Two-wire Serial Interface CharacteristicsTable 29-15 describes the requirements for devices connected to the 2-wire Serial Bus. TheATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface meets or exceeds these requirements under the notedconditions.Timing symbols refer to Figure 29-5.Table 29-15.Two-wire Serial Bus RequirementsSymbol Parameter Condition Min. Max UnitsV IL Input Low-voltage -0.5 0.3 V CC VV IH Input High-voltage 0.7 V CC V CC + 0.5 VV hys(1)Hysteresis of Schmitt Trigger Inputs 0.05 V CC(2)– VV OL(1)Output Low-voltage 3mA sink current 0 0.4 Vt r(1)Rise Time for both SDA and SCL 20 + 0.1C b(3)(2)300 nst of(1)Output Fall Time from V IHmin to V ILmax 10pF < C b < 400pF (3) 20 + 0.1C b(3)(2)250 nst SP(1)Spikes Suppressed by Input Filter 0 50 (2) nsI i Input Current each I/O Pin 0.1V CC < V i < 0.9V CC -10 10 µAC i(1)Capacitance for each I/O Pin – 10 pF(4)f SCL SCL Clock Frequency f CK > max(16f SCL , 250kHz) (5) 0 400 kHzf SCL ≤ 100kHzV CC– 0,4V 1000ns--------------------------- ---------------- Ω3mAC bRp Value of Pull-up resistorf SCL > 100kHzV CC– 0,4V---------------------------300ns------------- Ω3mAC bt HD;STAt LOWt HIGHt SU;STAt HD;DATt SU;DATt SU;STOt BUFHold Time (repeated) START ConditionLow Period of the SCL ClockHigh period of the SCL clockSet-up time for a repeated START conditionData hold timeData setup timeSetup time for STOP conditionBus free time between a STOP and STARTconditionf SCL ≤ 100kHz 4.0 – µsf SCL > 100kHz 0.6 – µsf SCL ≤ 100kHz 4.7 – µsf SCL > 100kHz 1.3 – µsf SCL ≤ 100kHz 4.0 – µsf SCL > 100kHz 0.6 – µsf SCL ≤ 100kHz 4.7 – µsf SCL > 100kHz 0.6 – µsf SCL ≤ 100kHz 0 3.45 µsf SCL > 100kHz 0 0.9 µsf SCL ≤ 100kHz 250 – nsf SCL > 100kHz 100 – nsf SCL ≤ 100kHz 4.0 – µsf SCL > 100kHz 0.6 – µsf SCL ≤ 100kHz 4.7 – µsf SCL > 100kHz 1.3 – µs8271D–AVR–05/11327
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Atmel Corporation2325 Orchard Parkw
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ATMega chip full datasheet - UCSD Department of Physics

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