ATMega chip full datasheet - UCSD Department of Physics

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ATmega48A/PA/88A/PA/168A/PA/328/PTable 2.Assembly Code Example C Example Comments1ldi r16,(1
ATmega48A/PA/88A/PA/168A/PA/328/P22.7 Transmission ModesThe TWI can operate in one of four major modes. These are named Master Transmitter (MT),Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of thesemodes can be used in the same application. As an example, the TWI can use MT mode to writedata into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other mastersare present in the system, some of these might transmit data to the TWI, and then SR modewould be used. It is the application software that decides which modes are legal.The following sections describe each of these modes. Possible status codes are describedalong with figures detailing data transmission in each of the modes. These figures contain thefollowing abbreviations:S: START conditionRs: REPEATED START conditionR: Read bit (high level at SDA)W: Write bit (low level at SDA)A: Acknowledge bit (low level at SDA)A: Not acknowledge bit (high level at SDA)Data: 8-bit data byteP: STOP conditionSLA: Slave AddressIn Figure 22-12 to Figure 22-18, circles are used to indicate that the TWINT Flag is set. Thenumbers in the circles show the status code held in TWSR, with the prescaler bits masked tozero. At these points, actions must be taken by the application to continue or complete the TWItransfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate softwareaction. For each status code, the required software action and details of the following serialtransfer are given in Table 22-2 to Table 22-5. Note that the prescaler bits are masked to zero inthese tables.22.7.1 Master Transmitter ModeIn the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver(see Figure 22-11). In order to enter a Master mode, a START condition must be transmitted.The format of the following address packet determines whether Master Transmitter or MasterReceiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,MR mode is entered. All the status codes mentioned in this section assume that theprescaler bits are zero or are masked to zero.8271D–AVR–05/11229
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Atmel Corporation2325 Orchard Parkw
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ATMega chip full datasheet - UCSD Department of Physics

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