ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PFigure 24-1.Analog to Digital Converter Block Schematic Operation,ADC CONVERSIONCOMPLETE IRQ8-BIT DATA BUSREFS1ADC MULTIPLEXERSELECT (ADMUX)REFS0ADLARMUX3MUX2MUX1MUX0ADENADIEADC CTRL. & STATUSREGISTER (ADCSRA)ADSCADFRADIF ADIFADPS2ADPS1ADPS015 0ADC DATA REGISTER(ADCH/ADCL)ADC[9:0]MUX DECODERPRESCALERAVCCAREFINTERNAL 1.1VREFERENCECHANNEL SELECTION10-BIT DACCONVERSION LOGICSAMPLE & HOLDCOMPARATOR-+TEMPERATURESENSORGNDBANDGAPREFERENCEADC7ADC6ADC5INPUTMUXADC MULTIPLEXEROUTPUTADC4ADC3ADC2ADC1ADC0The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC inputpins, as well as GND and a fixed bandgap voltage reference, can be selected as single endedinputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltagereference and input channel selections will not go into effect until ADEN is set. The ADCdoes not consume power when ADEN is cleared, so it is recommended to switch off the ADCbefore entering power saving sleep modes.The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH andADCL. By default, the result is presented right adjusted, but can optionally be presented leftadjusted by setting the ADLAR bit in ADMUX.If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to readADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the DataRegisters belongs to the same conversion. Once ADCL is read, ADC access to Data Registersis blocked. This means that if ADCL has been read, and a conversion completes before ADCH is8271D–AVR–05/11253