ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PFigure 11-1.Reset LogicDATA BUSMCU StatusRegister (MCUSR)Power-on ResetCircuitBrown-outBODLEVEL [2..0]Reset CircuitPull-up ResistorSPIKEFILTERRSTDISBLWatchdogOscillatorClock CK Delay CountersGeneratorTIMEOUTCKSEL[3:0]SUT[1:0]A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching thePower-on Reset threshold voltage invokes the delay counter, which determines how long thedevice is kept in RESET after V CC rise. The RESET signal is activated again, without any delay,when V CC decreases below the detection level.Figure 11-2. MCU Start-up, RESET Tied to V CCPORFBORFEXTRFWDRF11.3 Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection levelis defined in ”System and Reset Characteristics” on page 324. The POR is activated wheneverV CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, aswell as to detect a failure in supply voltage.VCCV POTRESETV RSTTIME-OUTt TOUTINTERNALRESET8271D–AVR–05/1149