ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/P14.4 Register Description14.4.1 MCUCR – MCU Control Register14.4.2 PORTB – The Port B Data RegisterBit 7 6 5 4 3 2 1 00x35 (0x55) – BODS (1) BODSE (1) PUD – – IVSEL IVCE MCUCRRead/Write R R/W R/W R/W R R R/W R/WInitial Value 0 0 0 0 0 0 0 0Notes: 1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P• Bit 4 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn andPORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Configuringthe Pin” on page 78 for more details about this feature.Bit 7 6 5 4 3 2 1 00x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTBRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 014.4.3 DDRB – The Port B Data Direction RegisterBit 7 6 5 4 3 2 1 00x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRBRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 014.4.4 PINB – The Port B Input Pins Address (1)Bit 7 6 5 4 3 2 1 00x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINBRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value N/A N/A N/A N/A N/A N/A N/A N/A14.4.5 PORTC – The Port C Data RegisterBit 7 6 5 4 3 2 1 00x08 (0x28) – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTCRead/Write R R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 014.4.6 DDRC – The Port C Data Direction RegisterBit 7 6 5 4 3 2 1 00x07 (0x27) – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRCRead/Write R R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 014.4.7 PINC – The Port C Input Pins Address (1)Bit 7 6 5 4 3 2 1 00x06 (0x26) – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINCRead/Write R R/W R/W R/W R/W R/W R/W R/WInitial Value 0 N/A N/A N/A N/A N/A N/A N/A8271D–AVR–05/1194