ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/P28.7.15 Parallel Programming CharacteristicsFor characteristics of the Parallel Programming, see ”Parallel Programming Characteristics” onpage 330.28.8 Serial DownloadingBoth the Flash and EEPROM memory arrays can be programmed using the serial SPI bus whileRESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output).After RESET is set low, the Programming Enable instruction needs to be executed firstbefore program/erase operations can be executed. NOTE, in Table 28-17 on page 313, the pinmapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internalSPI interface.Figure 28-7. Serial Programming and Verify (1)+1.8 - 5.5VMOSIMISOSCKVCCAVCC+1.8 - 5.5V (2)XTAL1RESETGNDNotes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to theXTAL1 pin.2. V CC - 0.3V < AV CC < V CC + 0.3V, however, AV CC should always be within 1.8 - 5.5VWhen programming the EEPROM, an auto-erase cycle is built into the self-timed programmingoperation (in the Serial mode ONLY) and there is no need to first execute the Chip Eraseinstruction. The Chip Erase operation turns the content of every memory location in both theProgram and EEPROM arrays into 0xFF.Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periodsfor the serial clock (SCK) input are defined as follows:Low: > 2 CPU clock cycles for f ck < 12MHz, 3 CPU clock cycles for f ck ≥ 12MHzHigh: > 2 CPU clock cycles for f ck < 12MHz, 3 CPU clock cycles for f ck ≥ 12MHz8271D–AVR–05/11312