ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/PFigure 29-6.Parallel Programming Timing, Including some General Timing RequirementsXTAL1t XHXLData & Contol(DATA, XA0/1, BS1, BS2)t DVXHt XLDXt XLWLt BVPH t PLBX t BVWLt WLBXPAGEL t PHPLWRRDY/BSYt PLWLt WLWHWLRLt WLRHFigure 29-7. Parallel Programming Timing, Loading Sequence with Timing Requirements (1)LOAD ADDRESS(LOW BYTE)LOAD DATA(LOW BYTE)LOAD DATA LOAD DATA(HIGH BYTE)LOAD ADDRESS(LOW BYTE)t XLXHt XLPHt PLXHXTAL1BS1PAGELDATAADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)XA0XA1Note: 1. The timing requirements shown in Figure 29-6 (i.e., t DVXH , t XHXL , and t XLDX ) also apply to loadingoperation.Figure 29-8.Parallel Programming Timing, Reading Sequence (within the Same Page) withTiming Requirements (1)LOAD ADDRESS(LOW BYTE)READ DATA(LOW BYTE)READ DATA(HIGH BYTE)LOAD ADDRESS(LOW BYTE)t XLOLXTAL1t BVDVBS1t OLDVOEt OHDZDATAADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)XA0XA1Note: 1. The timing requirements shown in Figure 29-6 (i.e., t DVXH , t XHXL , and t XLDX ) also apply to readingoperation.8271D–AVR–05/11331