ATMega chip full datasheet - UCSD Department of Physics

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ATmega48A/PA/88A/PA/168A/PA/328/Pand ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADCchannels.Figure 24-9.ADC Power ConnectionsGNDVCCPC5 (ADC5/SCL)PC4 (ADC4/SDA)PC3 (ADC3)PC2 (ADC2)PC1 (ADC1)PC0 (ADC0)ADC7GNDAREFADC6AVCC100nF Analog Ground Plane10µHPB524.6.3 ADC Accuracy DefinitionsAn n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps(LSBs). The lowest code is read as 0, and the highest code is read as 2 n -1.Several parameters describe the deviation from the ideal behavior:• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at0.5 LSB). Ideal value: 0 LSB.8271D–AVR–05/11260
ATmega48A/PA/88A/PA/168A/PA/328/PFigure 24-10. Offset ErrorOutput CodeIdeal ADCActual ADCOffsetErrorV REFInput Voltage• Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition(0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0LSBFigure 24-11. Gain ErrorOutput CodeGainErrorIdeal ADCActual ADCV REFInput Voltage• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximumdeviation of an actual transition compared to an ideal transition for any code. Ideal value: 0LSB.8271D–AVR–05/11261
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Atmel Corporation2325 Orchard Parkw
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ATMega chip full datasheet - UCSD Department of Physics

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