ATMega chip full datasheet - UCSD Department of Physics

ATmega48A/PA/88A/PA/168A/PA/328/P19. SPI – Serial Peripheral Interface19.1 Features19.2 Overview• Full-duplex, Three-wire Synchronous Data Transfer• Master or Slave Operation• LSB First or MSB First Data Transfer• Seven Programmable Bit Rates• End of Transmission Interrupt Flag• Write Collision Flag Protection• Wake-up from Idle Mode• Double Speed (CK/2) Master SPI ModeThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between theATmega48A/PA/88A/PA/168A/PA/328/P and peripheral devices or between several AVRdevices.The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 206. ThePRSPI bit in ”Minimizing Power Consumption” on page 43 must be written to zero to enable SPImodule.8271D–AVR–05/11168