ATMega chip full datasheet - UCSD Department of Physics

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ATmega48A/PA/88A/PA/168A/PA/328/PAssembly Code Examplein r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout SREG, r16 ; restore SREG value (I-bit)C Code Examplechar cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1
ATmega48A/PA/88A/PA/168A/PA/328/P8. AVR Memories8.1 OverviewThis section describes the different memories in the ATmega48A/PA/88A/PA/168A/PA/328/P.The AVR architecture has two main memory spaces, the Data Memory and the Program Memoryspace. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROMMemory for data storage. All three memory spaces are linear and regular.8.2 In-System Reprogrammable Flash Program MemoryThe ATmega48A/PA/88A/PA/168A/PA/328/P contains 4/8/16/32Kbytes On-chip In-SystemReprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32bits wide, the Flash is organized as 2/4/8/16K x 16. For software security, the Flash Programmemory space is divided into two sections, Boot Loader Section and Application Program Sectionin ATmega88PA and ATmega168PA. See SELFPRGEN description in section ”SPMCSR –Store Program Memory Control and Status Register” on page 295 for more details.The Flash memory has an endurance of at least 10,000 write/erase cycles. TheATmega48A/PA/88A/PA/168A/PA/328/P Program Counter (PC) is 11/12/13/14 bits wide, thusaddressing the 2/4/8/16K program memory locations. The operation of Boot Program sectionand associated Boot Lock bits for software protection are described in detail in ”Self-Programmingthe Flash, ATmega 48A/48PA” on page 271 and ”Boot Loader Support – Read-While-WriteSelf-Programming” on page 280. ”Memory Programming” on page 297 contains a detaileddescription on Flash Programming in SPI- or Parallel Programming mode.Constant tables can be allocated within the entire program memory address space (see the LPM– Load Program Memory instruction description).Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Timing”on page 14.8271D–AVR–05/1117
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Atmel Corporation2325 Orchard Parkw
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ATMega chip full datasheet - UCSD Department of Physics

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