Ultralow power ARM-based 32-bit MCU with 384 Kbytes Flash ... - Keil

Electrical characteristicsSTM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RDTable 35. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)Symbol Parameter Min Max Unitt w(NE) FSMC_NE low time TBD TBD nst v(NWE_NE) FSMC_NEx low to FSMC_NWE low TBD TBD nst w(NWE) FSMC_NWE low time TBD TBD nst h(NE_NWE) FSMC_NWE high to FSMC_NE high hold time T HCLK nst v(A_NE) FSMC_NEx low to FSMC_A valid TBD nst h(A_NWE) Address hold time after FSMC_NWE high T HCLK nst v(BL_NE) FSMC_NEx low to FSMC_BL valid TBD nst h(BL_NWE) FSMC_BL hold time after FSMC_NWE high TBD nst v(Data_NE) FSMC_NEx low to Data valid TBD nst h(Data_NWE) Data hold time after FSMC_NWE high T HCLK nst v(NADV_NE) FSMC_NEx low to FSMC_NADV low TBD nst w(NADV) FSMC_NADV low time TBD ns1. C L = 15 pF.2. Preliminary values.Figure 17.Asynchronous multiplexed PSRAM/NOR read waveformst w(NE)FSMC_NEt v(NOE_NE)t h(NE_NOE)FSMC_NOEt w(NOE)FSMC_NWEt v(A_NE)t h(A_NOE)FSMC_A[25:16]Addresst v(BL_NE)t h(BL_NOE)FSMC_NBL[1:0]NBLt h(Data_NE)t su(Data_NE)t v(A_NE)t su(Data_NOE)t h(Data_NOE)FSMC_AD[15:0]AddressDatat v(NADV_NE)t h(AD_NADV)t w(NADV)FSMC_NADVai14892b78/124 Doc ID 022268 Rev 2