Ultralow power ARM-based 32-bit MCU with 384 Kbytes Flash ... - Keil

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Electrical characteristicsSTM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RDFigure 24.Recommended NRST pin protection 1. The reset network protects the device against parasitic resets.2. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified inTable 50. Otherwise the reset will not be taken into account by the device.6.3.15 TIM timer characteristicsThe parameters given in the following table are guaranteed by design.Refer to Section 6.3.12: I/O current injection characteristics for details on the input/outputalternate function characteristics (output compare, input capture, external clock, PWMoutput).Table 51.TIMx (1) characteristicsSymbol Parameter Conditions Min Max Unitt res(TIM)f EXTTimer resolution timeTimer external clockfrequency on CH1 to CH41 t TIMxCLKf TIMxCLK = 32 MHz 31.25 ns0 f TIMxCLK /2 MHzf TIMxCLK = 32 MHz 0 16 MHzRes TIM Timer resolution 16 bitt COUNTERt MAX_COUNT16-bit counter clock periodwhen internal clock isselected (timer’s prescalerdisabled)Maximum possible count1 65536 t TIMxCLKf TIMxCLK = 32 MHz 0.0312 2048 µs65536 × 65536 t TIMxCLKf TIMxCLK = 32 MHz 134.2 s1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.94/124 Doc ID 022268 Rev 2
STM32L162VD, STM32L162ZD, STM32L162QD, STM32L162RDElectrical characteristics6.3.16 Communications interfacesI 2 C interface characteristicsUnless otherwise specified, the parameters given in Table 52 are derived from testsperformed under ambient temperature, f PCLK1 frequency and V DD supply voltage conditionssummarized in Table 10.The STM32L162xD product line I 2 C interface meets the requirements of the standard I 2 Ccommunication protocol with the following restrictions: SDA and SCL are not “true” opendrainI/O pins. When configured as open-drain, the PMOS connected between the I/O pinand V DD is disabled, but is still present.The I 2 C characteristics are described in Table 52. Refer also to Section 6.3.12: I/O currentinjection characteristics for more details on the input/output alternate function characteristics(SDA and SCL).Table 52.I 2 C characteristicsSymbolParameterStandard mode I 2 C (1)Fast mode I 2 C (1)(2)Min Max Min MaxUnitt w(SCLL) SCL clock low time 4.7 1.3t w(SCLH) SCL clock high time 4.0 0.6t su(SDA) SDA setup time 250 100t h(SDA) SDA data hold time 0 (3)0 (4)900 (3)µst r(SDA)t r(SCL)SDA and SCL rise time 1000 20 + 0.1C b 300nst f(SDA) SDA and SCL fall time 300 300t f(SCL)t h(STA) Start condition hold time 4.0 0.6t su(STA)Repeated Start conditionµs4.7 0.6setup timet su(STO) Stop condition setup time 4.0 0.6 μst w(STO:STA)Stop to Start condition time(bus free)4.7 1.3 μsC bCapacitive load for each busline1. Guaranteed by design, not tested in production.400 400 pF2. f PCLK1 must be higher than 2 MHz to achieve standard mode I²C frequencies. It must be higher than 4 MHzto achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²Cfast mode clock.3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the lowperiod of SCL signal.4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge theundefined region of the falling edge of SCL.Doc ID 022268 Rev 2 95/124
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STM32L162VD STM32L162ZDSTM32L162QD
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STM32L162VD, STM32L162ZD, STM32L162
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List of tablesSTM32L162VD, STM32L16
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Functional overviewSTM32L162VD, STM
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Functional overviewSTM32L162VD, STM
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Pin descriptionsSTM32L162VD, STM32L
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Ultralow power ARM-based 32-bit MCU with 384 Kbytes Flash ... - Keil

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