DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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sysIO Differential Electrical Characteristics LVDS Emulation 14 Platform Manager Data Sheet FPGA section outputs can support LVDS outputs via emulation (LVDS25E), in addition to the LVDS support that is available. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3 is one possible solution for LVDS standard implementation. Resistor values in Figure 3 are industry standard values for 1% resistors. Figure 3. LVDS Using External Resistors (LVDS25E) BLVDS Emulation FPGA outputs support the BLVDS standard through emulation. The output is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 4 is one possible solution for bi-directional multi-point differential signals. Figure 4. BLVDS Multi-point Output Example 2.5V 16mA 16mA 2.5V + - LVPECL Emulation VCCIO = 2.5 8mA VCCIO = 2.5 8mA 158 158 140 Zo = 100 Internal Emulated LVDS Buffer External External Internal Note: All resistors are ±1%. Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 80 80 45-90 ohms 45-90 ohms 80 80 2.5V 2.5V - 2.5V 2.5V 16mA 16mA 16mA 16mA + FPGA outputs support the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The scheme shown in Figure 5 is one possible solution for point-to-point signals. . . . 80 80 100 80 + - + - 2.5V 16mA 2.5V 16mA + -
Figure 5. Differential LVPECL 15 Platform Manager Data Sheet For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet. RSDS Emulation V CCIO = 3.3V 16mA V CCIO = 3.3V 16mA 100 ohms 100 ohms FPGA outputs support the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The scheme shown in Figure 6 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 6 are industry standard values for 1% resistors. Figure 6. RSDS (Reduced Swing Differential Standard) Oscillator Transient Characteristics 100 ohms Transmission line, Zo = 100 ohm differential Internal External External Internal VCCIO = 2.5V 8mA VCCIO = 2.5V 8mA 294 294 150 ohms Internal External External Internal Emulated RSDS Buffer 121 Zo = 100 Over Recommended Operating Conditions Symbol Parameter Power Management inter- Conditions Min. Typ. Max. Units fCLK nal master clock frequency (MCLK) 7.6 8 8.4 MHz fCLKEXT Power Management externally applied master clock (MCLK) 7.2 8.8 MHz fPLDCLK CPLDCLK output frequency fCLK = 8MHz 250 kHz fFPGACLK FPGA internal master clock frequency 18 26 MHz 100 + - + -
Page 1 and 2: February 2012 Data Sheet DS1036 Fea
Page 3 and 4: Figure 1. Typical Platform Manager
Page 5 and 6: Recommended Operating Conditions 1,
Page 7 and 8: ESD Performance All pins Pin Group
Page 9 and 10: 1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13: sysIO Recommended Operating Conditi
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
Page 59 and 60: 59 Platform Manager Data Sheet The
Page 61 and 62: Figure 46. Group of Six Programmabl
Page 63 and 64: 63 Platform Manager Data Sheet bank
Page 65 and 66:
Table 20. Characteristics of Normal
Page 67 and 68:
Figure 50. Platform Manager Alterna
Page 69 and 70:
Overview 69 Platform Manager Data S
Page 71 and 72:
Table 22. Power Management Section
Page 73 and 74:
73 Platform Manager Data Sheet CFG_
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75 Platform Manager Data Sheet Leav
Page 77 and 78:
Pin Descriptions and Logic Signal C
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Pin Descriptions and Logic Signal C
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Part Number Description Device Fami
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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