DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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2 Platform Manager Data Sheet The board power management function can be implemented using an internal 48-macrocell CPLD. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs (open-drain as well as HVOUT) may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32 �s to 2 seconds. The Platform Manager device incorporates up to eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The internal 10-bit A/D converter can both be used to monitor the VMON voltage through the I 2 C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the Platform Manager device. The FPGA section of the Platform Manager is optimized to meet the requirements of board management functions including reset distribution, boundary scan management, fault logging, FPGA load control, and system bus interface. The FPGA section uses look-up tables (LUTs) and distributed memories for flexible and efficient logic implementation. This instant-on capability enables the Platform Manager devices to integrate control functions that are required as soon as power is applied to the board. Power management functions can be integrated into the CPLD and digital board management functions can be integrated into the FPGA using the LogiBuilder tool provided by PAC-Designer ® software. In addition, the FPGA designs can also be implemented in VHDL or Verilog HDL through the ispLEVER ® software design tool. The Platform Manager IC supports a hardware I 2 C/SMBus slave interface that can be used to measure voltages through the Analog to Digital Converter or is used for trimming and margining using a microcontroller. There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to configure the FPGA portion of the device. The FPGA configuration memory can be changed in-system without interrupting the operation of the board management section. However, the Power Management section of the platform Manager cannot be changed without interrupting the power management operation. Table 1. Platform Manager Family Selection Table Parameter LPTM10-1247 LPTM10-12107 Analog Inputs 12 12 Margin and Trim 6 8 Total I/O 47 107 CPLD Macrocells 48 48 FPGA LUTs 640 640 Package 128-pin TQFP 208-ball ftBGA
Figure 1. Typical Platform Manager Application SPI Memory 12V Backplane Vin VID 4 I 2 C Interface CPU_ Reset 4 SPI Port 12V Current Monitor Platform Manager Processor Interface 3 Hot-Swap FET Control Margin & Trim Platform Manager Data Sheet Note: See reference design, IP documentation and application notes for more information on implementation of individual functions called out above. 3.3V 1.2V 1.0V Supply Sequencing Voltage Monitoring Reset Distribution
Page 1: February 2012 Data Sheet DS1036 Fea
Page 5 and 6: Recommended Operating Conditions 1,
Page 7 and 8: ESD Performance All pins Pin Group
Page 9 and 10: 1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13 and 14: sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
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53 Platform Manager Data Sheet Desi
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Figure 40. PFU Diagram Slice Slice
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57 Platform Manager Data Sheet Mode
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59 Platform Manager Data Sheet The
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Figure 46. Group of Six Programmabl
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63 Platform Manager Data Sheet bank
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Table 20. Characteristics of Normal
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Figure 50. Platform Manager Alterna
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Overview 69 Platform Manager Data S
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Table 22. Power Management Section
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73 Platform Manager Data Sheet CFG_
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75 Platform Manager Data Sheet Leav
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Pin Descriptions and Logic Signal C
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Pin Descriptions and Logic Signal C
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Part Number Description Device Fami
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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