DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

Figure 44. FPGA Secondary Clocks
PIO Groups
12
Routing Clock
Pads
60
Platform Manager Data Sheet
FPGA PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO
cells. PIO groups with four I/Os are placed on the left and right sides of the device while PIO groups with six I/Os are
placed on the top and bottom. The individual PIO cells are connected to their respective sysIO buffers and pads.
Two adjacent PIOs can be joined to provide a complementary output driver pair. The I/O pin pairs are labeled as “T”
and “C” to distinguish between the true and complement pins.
Figure 45. Group of Four Programmable I/O Cells
4
Four PIOs
16:1
16:1
16:1
16:1
This structure is used on the
left and right portion of the FPGA
PIO A
PIO B
PIO C
PIO D
Secondary (Control)
Clocks
PADA "T"
PADB "C"
PADC "T"
PADD "C"