DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

37
Platform Manager Data Sheet
DAC Register I 2 C on the fly to set the trimming voltage to a desired value. The DAC Register I 2 C is a volatile register
and is reset to 80H (DAC at Bipolar zero) upon power-on. The external microcontroller writes the correct DAC
code in this DAC Register I 2 C before enabling the programmable power supply.
Digital Closed Loop Trim Mode
Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a
desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of
the DC-DC converter with the internally stored voltage setpoint. The difference between the setpoint and the actual
DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output voltage
toward the setpoint. This operation iterates until the setpoint and the DC-DC converter voltage are equal.
Figure 20 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update
Rate Control register) the Platform Manager device initiates the closed loop power supply voltage correction cycle
through the following blocks:
Non-volatile Setpoint register stores the desired output voltage
Internal ADC is used to measure the voltage of the DC-DC converter
Tri-state comparator is used to compare the measured voltage from the ADC with the Setpoint register
contents. The output of the tri-state comparator can be one of the following:
+1 if the setpoint voltage is greater than the DC-DC converter voltage
-1 if the setpoint voltage is less than the DC-DC converter voltage
0 if the setpoint voltage is equal to the DC-DC converter voltage
Channel polarity control determines the polarity of the error signal
Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage.
The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity
and the tri-state comparator output. If the tri-state comparator output is 0, the closed loop trim register
contents are left unchanged.
The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter
output voltage.
Figure 20. Digital Closed Loop Trim Operation
Tri-State
Digital
Compare
(+1/0/-1)
Setpoint
(E 2 CMOS)
Platform Manager
E2 Channel
Polarity
CMOS Registers
(E2 DAC Register 3
TrimCell
CMOS) DAC Register 2
DAC Register 1
DAC Register 0
DAC
TRIMx
DAC Register I2C Profile Control
(CPLD)
+/-1
Update
Rate
Control
CPLD_CLT_EN
Closed Loop
Trim Register
Profile 0 Mode
Control (E 2 CMOS)
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following
table lists the programmable update interval that can be selected by the update rate register.
ADC
VMONx
TRIMIN
VOUT
GND
DC-DC
Converter