DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

ESD Performance
All pins
Pin Group ESD Stress Min. Units
1, 2, 3, 4
DC Electrical Characteristics
1, 2
FPGA Supply Current (Sleep Mode)
HBM 1500 V
CDM 1000 V
7
Platform Manager Data Sheet
Symbol Parameter Conditions Typ. 5
Max. Units
PICC Power Management section supply current Normal operation 40 mA
PICCINP Power Management section supply current Normal operation 5 mA
PICCJ Power Management section supply current Normal operation 1 mA
1 ICC FPGA Core Power Supply 8.7 mA
ICCAUX FPGA Auxiliary Power Supply
VCCAUX = 3.3V
During initialization (0MHz) 7 mA
ICCIO FPGA Bank Power Supply 6
During initialization (0MHz) 2.4 mA
1. For further information on FPGA section supply current, please see details of additional technical documentation at the end of this data
sheet.
2. Assumes all FPGA section I/O pins are held at VCCIO or GND.
3. FPGA Frequency = 0 MHz.
4. Typical FPGA user pattern.
5. TJ = 25oC, power supplies at nominal voltage.
6. Per bank, VCCIO = 2.5V. Does not include pull-up/pull-down.
Symbol Parameter Conditions Typ. 3
Max. Units
1 ICC FPGA Core Power Supply Sleep Mode 12 25 µA
ICCAUX FPGA Auxiliary Power Supply 1 25 µA
ICCIO Bank Power Supply 4
2 30 µA
1. Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND.
2. Frequency = 0MHz.
3. TA = 25°C, power supplies at nominal voltage.
4. Per bank.