DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

Figure 18. Voltage Profile Control
Voltage Profile
Set to 00
CPLD Control Signals
CPLD_VPS[0:1]
2
2
INT/EXT
SELECT
(E 2 CMOS)
CTRL
MUX
2
Common Voltage Profile Control Signals
Common Voltage Profile Control Signals
35
Platform Manager
Margin/Trim Block
TrimCell
#1*
TrimCell
#2*
TrimCell
#3
TrimCell
#4
TrimCell
#5
TrimCell
#6
TrimCell
#7
TrimCell
#8
*TrimCell #1 and TrimCell #2 (Trim 1 and Trim 2) are not available in the 128-pin TQFP package option.
Platform Manager Data Sheet
TrimCell Architecture
The TrimCell block diagram is shown in Figure 19. The 8-bit DAC at the output provides the trimming voltage
required to set the output voltage of a programmable supply. Each TrimCell can be operated in any one of the four
voltage profiles. In each voltage profile the output trimming voltage can be set to a preset value. There are six 8-bit
registers in each TrimCell that, depending on the operational mode, set the DAC value. Of these, four DAC values
(DAC Register 0 to DAC Register 3) are stored in the E 2 CMOS memory while the remaining register contents are
stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC.
The Profile Mux can be controlled by common TrimCell voltage profile control signals.
Trim 1
Trim 2
Trim 3
Trim 4
Trim 5
Trim 6
Trim 7
Trim 8