DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Platform Manager Data Sheet
The UES word may also be read through the I 2 C interface, with the register mapping shown in Figure 34.
Figure 34. I 2 C Register Mapping for UES Bits
The I 2 C interface also provides the ability to initiate reset operations. The Platform Manager may be reset by issuing
a write of any value to the I 2 C RESET register (Figure 35). Note: The execution of the I 2 C reset command is
equivalent to toggling the Resetb pin of the device. Refer to the Resetb Signal, RESET Command via JTAG or I 2 C
section of this data sheet for further information.
Figure 35. I 2 C Reset Register
0x0A - UES_BYTE0 (Read Only)
UES7 UES6 UES5 UES4 UES3 UES2 UES1 UES0
b7 b6 b5 b4 b3 b2 b1 b0
0x0B - UES_BYTE1 (Read Only)
UES15 UES14 UES13 UES12 UES11 UES10 UES9 UES8
b7 b6 b5 b4 b3 b2 b1 b0
0x0C - UES_BYTE2 (Read Only)
UES23 UES22 UES21 UES20 UES19 UES18 UES17 UES16
b7 b6 b5 b4 b3 b2 b1 b0
0x0D - UES_BYTE3 (Read Only)
UES31 UES30 UES29 UES28 UES27 UES26 UES25 UES24
b7 b6 b5 b4 b3 b2 b1 b0
0x12 - RESET (Write Only)
X X X X X X X X
b7 b6 b5 b4 b3 b2 b1
b0