DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Figure 47. PIO Block Diagram sysIO Buffer From Routing From Routing 62 Platform Manager Data Sheet Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL. FPGA output buffers and ratioed input buffers (LVTTL and LVCMOS) are powered using V CCIO . In addition to the bank V CCIO supplies, the FPGA fabric has a V CC core logic power supply, and a V CCAUX supply that powers up a variety of internal circuits. Top and Bottom sysIO Buffer Pairs The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom of the devices also support differential input buffers. Left and Right sysIO Buffer Pairs Fast Output Data signal DO Input Data Signal Note: Buffer 1 tracks with VCCAUX Buffer 2 tracks with VCCIO. Buffer 3 tracks with internal 1.2V VREF . The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Typical I/O Behavior During Power-up Programmable Delay Elements The internal power-on-reset (POR) signal is deactivated when V CC and V CCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all V CCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O TS sysIO Buffer 1 2 3 TO PAD
63 Platform Manager Data Sheet banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-up to V CCIO . The I/O pins will maintain the blank configuration until V CC , V CCAUX and V CCIO have reached satisfactory levels at which time the I/Os will take on the user-configured settings. The V CC and V CCAUX supply the power to the FPGA core fabric, whereas the V CCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers should be powered up along with the FPGA core fabric. Therefore, V CCIO supplies should be powered up together with the V CC and V CCAUX supplies. (V CC and V CCAUX must be physically tied together for proper operation). Supported Standards The FPGA sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL output emulation is also supported. Tables 18 and 19 show the I/O standards (together with their supply and reference voltages) supported by the FPGA I/Os. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet. Note: I/O bank 2 pins do not support LVCMOS12, LVCMOS15 or LVCMOS18 standards. Table 18. Supported Input Standards Table 19. Supported Output Standards VCCIO (Typ.) Input Standard 3.3V 2.5V 1.8V 1 1.5V 1 Single Ended Interfaces LVTTL X X X X X LVCMOS33 X X X X X LVCMOS25 X X X X X LVCMOS18 X LVCMOS15 X LVCMOS12 1. Not supported by I/O Bank 2 (VCCIO2 ). X X X X X 1.2V 1 Output Standard Single-ended Interfaces Drive VCCIO (Typ.) LVTTL 4mA, 8mA, 12mA, 16mA 3.3 LVCMOS33 4mA, 8mA, 12mA, 14mA 3.3 LVCMOS25 4mA, 8mA, 12mA, 14mA 2.5 LVCMOS18 1 4mA, 8mA, 12mA, 14mA 1.8 LVCMOS15 1 4mA, 8mA 1.5 LVCMOS12 1 2mA, 6mA 1.2 LVCMOS33, Open Drain 4mA, 8mA, 12mA, 14mA — LVCMOS25, Open Drain 4mA, 8mA, 12mA, 14mA — LVCMOS18, Open Drain1 4mA, 8mA, 12mA, 14mA — LVCMOS15, Open Drain 1 4mA, 8mA — LVCMOS12, Open Drain1 1. Not supported by I/O Bank 2 (VCCIO2). 2mA, 6mA —
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February 2012 Data Sheet DS1036 Fea
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Figure 1. Typical Platform Manager
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Recommended Operating Conditions 1,
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ESD Performance All pins Pin Group
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1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13 and 14: sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
Page 59 and 60: 59 Platform Manager Data Sheet The
Page 61: Figure 46. Group of Six Programmabl
Page 65 and 66: Table 20. Characteristics of Normal
Page 67 and 68: Figure 50. Platform Manager Alterna
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79 and 80: Pin Descriptions and Logic Signal C
Page 81: Part Number Description Device Fami
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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