DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Figure 49. Platform Manager JTAG Interconnection Configuration Diagram APS TMS TDO TDI TCK TDISEL Board 3.3V To Other Board Devices Programming Platform Manager: Alternate Method 66 Platform Manager Data Sheet Some applications require that the Platform Manager be programmed before turning the power on to the entire circuit board. To meet such application needs, the Platform Manager provides an alternate programming method which enables the programming of the Platform Manager device through the JTAG chain with a separate power supply applied just to the programming section of the Platform Manager device with the main power supply of the board turned off. Three special purpose pins, APS, PATDI and PTDISEL, enable programming of the un-programmed Platform Manager under such circumstances. The APS pin provides power to the programming circuitry of the Platform Manager device (when PVCCD and PVCCA are unpowered). The PVCCJ pin must be powered to enable the JTAG port. The PATDI pin provides an alternate connection to the JTAG header while bypassing all the un-powered devices in the JTAG chain. PTDISEL pin enables switching between the PATDI and the standard JTAG signal PTDI. When the internally pulled-up PTDISEL = 1, standard PTDI pin is enabled and when the PTDISEL = 0, PATDI is enabled. In order to use this feature the JTAG signals of the Platform Manager are connected to the header as shown in Figure 50. Note: The Platform Manager should be the last device in the JTAG chain. After programming, the APS pin MUST be left floating when the PVCCD and PVCCA pins are powered. Alternate PTDI Selection Via JTAG Command FTCK Other VCC FTDO FTDI FTMS VCCIO2 Platform Manager When the PTDISEL pin held high and four consecutive IDCODE instructions are issued, Platform Manager responds by making its active JTAG data input the PATDI pin. When PATDI is selected, data on its PTDI pin is ignored until the JTAG state machine returns to the Test-Logic-Reset state. This method of selecting PATDI takes advantage of the fact that a JTAG device with an IDCODE register will automatically load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG capability permits blind interrogation of devices so that their location in a serial chain can be identified without having to know anything about them in advance. A blind interrogation can be made using only the PTMS and PTCK control pins, which means PTDI and PTDO are not required for performing the operation. Figure 50 illustrates the logic for selecting whether the PTDI or PATDI pin is the active data input to Platform Manager. PTCK APS PTDI PVCCA/D PTDO PVCCJ PTMS PATDI PTDISEL From Other Board Devices
Figure 50. Platform Manager Alternate PTDI Configuration Diagram APS TMS TDO TDI TCK TDISEL Figure 51. Power Manager PTDI/PATDI Pin Selection Diagram PTDI PATDI To Other Board Devices 1 0 Board 3.3V FTCK Other VCC FTDO FTDI FTMS Test-Logic-Reset SET PTDISEL Q CLR VCCIO2 67 Platform Manager PTMS PTCK Platform Manager Data Sheet Table 21 shows in truth table form the same conditions required to select either PTDI or PATDI as in the logic diagram found in Figure 50. JTAG Platform Manager PTCK APS PTDI 4 Consecutive IDCODE Instructions Loaded at Update-IR PVCCA/D PTDO PVCCJ PTMS PATDI PTDISEL From Other Board Devices PTDO
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February 2012 Data Sheet DS1036 Fea
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Figure 1. Typical Platform Manager
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Recommended Operating Conditions 1,
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ESD Performance All pins Pin Group
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1, 2, 3, 4 Programming and Erase Su
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ADC Characteristics ADC Error Budge
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sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
Page 59 and 60: 59 Platform Manager Data Sheet The
Page 61 and 62: Figure 46. Group of Six Programmabl
Page 63 and 64: 63 Platform Manager Data Sheet bank
Page 65: Table 20. Characteristics of Normal
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79 and 80: Pin Descriptions and Logic Signal C
Page 81: Part Number Description Device Fami
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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