DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Platform Manager Data Sheet
Designs using the SMBAlert feature are required to set the device’s I 2 C/SMBus address to the lowest of all the
addresses on that I 2 C/SMBus.
RESETb Signal, RESET Command via JTAG or I 2 C
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG or I 2 C will
force the outputs to the following states independent of how these outputs have been configured in the PINS window:
OUT5-16 will go high-impedance.
HVOUT pins programmed for open drain operation will go high-impedance.
HVOUT pins programmed for FET driver mode operation will pull down.
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, ADCs, and DACs will not be operational until 2.5 milliseconds (max.) after
the conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the Platform
Manager device operation, results in the device aborting all operations and returning to the power-on reset state.
The status of the power supplies which are being enabled by the Platform Manager will be determined by the state
of the outputs shown above.