DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Figure 41. Slice Diagram From Routing Control Signals selected and inverted per Slice in routing A1 B1 C1 D1 M1 M0 A0 B0 C0 D0 CE CLK LSR Table 14. Slice Signal Descriptions To Adjacent Slice/PFU CO LUT4 & CARRY CI CO LUT4 & CARRY CI F SUM F SUM From Adjacent Slice/PFU Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell. 56 Platform Manager Data Sheet Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0/M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice Output Inter-PFU signal FCO Fast Carry Out1 1. See Figure 40 for connection details. 2. Requires two PFUs. OFX0 LUT Expansion Mux Slice D FF/ Latch D FF/ Latch OFX1 F1 Fast Connection to I/O Cell* Q1 OFX0 Fast Connection to I/O Cell* F0 Q0 To Routing
57 Platform Manager Data Sheet Modes of Operation Each slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The slice in the PFF is capable of all modes except RAM. Table 15 lists the modes and the capability of the slice blocks. Table 15. Slice Modes Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SP 16x2 ROM 16x1 x 2 PFF Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit N/A ROM 16x1 x 2 Logic Mode: In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables (LUT4). A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals, Carry Generate and Carry Propagate, are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory. Through the combination of LUTs and slices, a variety of different memories can be constructed. The Platform Manager design tool supports the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 16 shows the number of slices required to implement different distributed RAM primitives. Figure 42 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two slices. One slice functions as the read-write port, while the other companion slice supports the read-only port. For more information on RAM mode in the FPGA section, please see details of additional technical documentation at the end of this data sheet. Table 16. Number of Slices Required For Implementing Distributed RAM SPR16x2 DPR16x2 Number of Slices 1 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM
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February 2012 Data Sheet DS1036 Fea
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Figure 1. Typical Platform Manager
Page 5 and 6: Recommended Operating Conditions 1,
Page 7 and 8: ESD Performance All pins Pin Group
Page 9 and 10: 1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13 and 14: sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55: Figure 40. PFU Diagram Slice Slice
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Page 61 and 62: Figure 46. Group of Six Programmabl
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Page 65 and 66: Table 20. Characteristics of Normal
Page 67 and 68: Figure 50. Platform Manager Alterna
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79 and 80: Pin Descriptions and Logic Signal C
Page 81: Part Number Description Device Fami
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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