DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Figure 32. I 2 C Digital Input Interface IN1 IN[2..4] USERJTAG Bit CPLD Output/Input_Value Register Select (E 2CMOS Configuration) 3 3 Input_Value MUX MUX 0x06 - INPUT_STATUS (Read Only) I 2C Interface Unit 48 Input_Status *I5 and I6 are internal inputs to the CPLD that can only be configured by writing them via the I 2 C interface (no external pin connection). Platform Manager Data Sheet The CPLD digital outputs may also be monitored and controlled through the I 2 C interface, as shown in Figure 33. The status of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[2:0] register. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive the pin, and does not sample the actual level present on the output pin. For example, if an output is set high but is not pulled up, the output status bit corresponding with that pin will read ‘1’, but a high output signal will not appear on the pin. Digital inputs I5 and I6 are only accessible via the I 2 C interface. In other words, there are no external pin connections to these two inputs. Digital outputs may also be optionally controlled directly by the I 2 C bus instead of by the CPLD array. The outputs may be driven either from the CPLD ORP or from the contents of the GP_OUTPUT[2:0] registers with the choice user-settable in E 2 CMOS memory. Each output may be independently set to output from the CPLD or from the GP_OUTPUT registers. 4 3 3 CPLD Array X X X X IN4 IN3 IN2 IN1 b7 b6 b5 b4 b3 b2 b1 b0 0x11 - INPUT_VALUE (Read/Write) X X I6* I5* I4 I3 I2 X b7 b6 b5 b4 b3 b2 b1 b0
Figure 33. I 2 C Output Monitor and Control Logic CPLD Output Routing Pool CPLD Output/GP_Output Register Select (E 2CMOS Configuration) 16 16 GP_Output1 GP_Output2 GP_Output3 16 MUX I 2C Interface Unit 0x03 - OUTPUT_STATUS0 (Read Only) Output_Status0 Output_Status1 Output_Status2 49 16 16 Platform Manager Data Sheet HVOUT[1..4] OUT[5..16] OUT8 OUT7 OUT6 OUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 b7 b6 b5 b4 b3 b2 b1 b0 0x04 - OUTPUT_STATUS1 (Read Only), 208-ball ftBGA package option X OUT12 OUT11 X OUT10 OUT9 X X b7 b6 b5 b4 b3 b2 b1 b0 0x05 - OUTPUT_STATUS2 (Read Only), 208-ball ftBGA package option X X X X OUT16 OUT15 OUT14 OUT13 b7 b6 b5 b4 b3 b2 b1 b0 0x04 - OUTPUT_STATUS1 (Read Only), 128-pin TQFP package option OUT14 X X OUT13 OUT10 OUT9 OUT11 OUT12 b7 b6 b5 b4 b3 b2 b1 b0 0x05 - OUTPUT_STATUS2 (Read Only), 128-pin TQFP package option X X X X OUT16 OUT15 X X b7 b6 b5 b4 b3 b2 b1 b0 0x0E - GP_OUTPUT1 (Read/Write) GP8 GP7 GP6 GP5_ENb GP4 GP3 GP2 GP1 b7 b6 b5 b4 b3 b2 b1 b0 0x0F - GP_OUTPUT2 (Read/Write), 208-ball ftBGA package option X GP12 GP11 X GP10 GP9 X X b7 b6 b5 b4 b3 b2 b1 b0 0x10 - GP_OUTPUT3 (Read/Write), 208-ball ftBGA package option X X X X GP16 GP15 GP14 GP13 b7 b6 b5 b4 b3 b2 b1 b0 0x0F - GP_OUTPUT2 (Read/Write), 128-pin TQFP package option GP14 X X GP13 GP10 GP9 GP11 GP12 b7 b6 b5 b4 b3 b2 b1 b0 0x10 - GP_OUTPUT3 (Read/Write), 128-pin TQFP package option X X X X GP16 GP15 X X b7 b6 b5 b4 b3 b2 b1 b0
Page 1 and 2: February 2012 Data Sheet DS1036 Fea
Page 3 and 4: Figure 1. Typical Platform Manager
Page 5 and 6: Recommended Operating Conditions 1,
Page 7 and 8: ESD Performance All pins Pin Group
Page 9 and 10: 1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13 and 14: sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47: Table 13. V MON Address Selection T
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
Page 59 and 60: 59 Platform Manager Data Sheet The
Page 61 and 62: Figure 46. Group of Six Programmabl
Page 63 and 64: 63 Platform Manager Data Sheet bank
Page 65 and 66: Table 20. Characteristics of Normal
Page 67 and 68: Figure 50. Platform Manager Alterna
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79 and 80: Pin Descriptions and Logic Signal C
Page 81: Part Number Description Device Fami

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