DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Pin Descriptions and Logic Signal Connections (Cont.) Thermal Management 80 Platform Manager Data Sheet Ball/Pin Function 208-Ball ftBGA 128-Pin TQFP Bank Dual Function Differential VMON8 H16 81 VMON9GS G15 VMON9 G16 83 VMON10GS F15 VMON10 F16 84 VMON11GS E15 VMON11 E16 86 VMON12GS D15 VMON12 D16 88 1. Primary clock inputs are single-ended. 2. Ensure that SLEEPN is tied to VCC via an external pull-up when the function will not be used or the Platform Manager FPGA section will not function correctly. 3. VCC and VCCAUX pins must be physically tied together for proper device operation. 4. PVCCA and PVCCD pins must be physically tied together for proper device operation. 5. PATDI pin is the alternate JTAG Test Data In, PTDISEL Pin = 0. 6. PTDI pin is the main JTAG Test Data In, PTDISEL Pin = 1. 7. This pin selects the JTAG Test Data Input pin PTDI/PATDI. 8. This pin has an internal pull-up. Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values.
Part Number Description Device Family Platform Manager Analog Inputs Digital I/Os 47 = 47 Digital I/Os 107 = 107 Digital I/Os Ordering Information Halogen-Free (RoHS Compliant) Packaging For Further Information 81 Platform Manager Data Sheet Part Number Package Pins/Balls Temp. LPTM10-1247-3TG128C TQFP 128 COM LPTM10-1247-3TG128I TQFP 128 IND LPTM10-12107-3FTG208C ftBGA 208 COM LPTM10-12107-3FTG208I ftBGA 208 IND For further information, refer to the following MachXO-specific literature which also applies to Platform Manager: TN1086, MachXO JTAG Programming and Configuration User’s Guide TN1090, Power Estimation and Management for MachXO Devices TN1091, MachXO sysIO Usage Guide – Power Calculator tool included with the Platform Manager design tools, or as a standalone download from � www.latticesemi.com/software TN1223, Using Platform Manager Successfully – Guidelines for practical circuits using Platform Manager Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com Revision History LPTM10 – 12 XXX – 3 XXG XXX X Grade C = Commercial I = Industrial Package TG128 = 128-pin Halogen-Free (RoHS Compliant) TQFP FTG208 = 208-ball Halogen-Free (RoHS Compliant) ftBGA Speed Date Version Change Summary October 2010 01.0 Initial release. December 2010 01.1 Typographical changes and clarifications. February 2012 01.2 Added footnotes 5-8 to Pin Descriptions and Logic Signal Connections table. February 2012 01.3 Updated document with new corporate logo.
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February 2012 Data Sheet DS1036 Fea
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Figure 1. Typical Platform Manager
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Recommended Operating Conditions 1,
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ESD Performance All pins Pin Group
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1, 2, 3, 4 Programming and Erase Su
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ADC Characteristics ADC Error Budge
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sysIO Recommended Operating Conditi
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Figure 5. Differential LVPECL 15 Pl
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Timing for Power Management JTAG Op
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Typical FPGA Building Block Functio
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FPGA Section Internal Timing Parame
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Flash Download Time FPGA JTAG Port
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FPGA Output Switching Test Conditio
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AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31 and 32: 31 Platform Manager Data Sheet VMON
Page 33 and 34: Figure 16. Platform Manager Trim an
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
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Page 61 and 62: Figure 46. Group of Six Programmabl
Page 63 and 64: 63 Platform Manager Data Sheet bank
Page 65 and 66: Table 20. Characteristics of Normal
Page 67 and 68: Figure 50. Platform Manager Alterna
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79: Pin Descriptions and Logic Signal C
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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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