DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
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Figure 46. Group of Six Programmable I/O Cells<br />
PIO<br />
Six PIOs<br />
This structure is used on the top<br />
and bottom portion of the devices<br />
PIO A<br />
PIO B<br />
PIO C<br />
PIO D<br />
PIO E<br />
PIO F<br />
61<br />
<strong>Platform</strong> <strong>Manager</strong> <strong>Data</strong> <strong>Sheet</strong><br />
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks<br />
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast<br />
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 47 shows<br />
the FPGA PIO logic.<br />
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the FPGA<br />
fabric. In addition there are programmable elements that can be utilized by the design tools to avoid positive hold<br />
times.<br />
PADA "T"<br />
PADB "C"<br />
PADC "T"<br />
PADD "C"<br />
PADE "T"<br />
PADF "C"
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