DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

RESET – This instruction resets the CPLD sequence and output macrocells.
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Platform Manager Data Sheet
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input 'IN1.' The CPLD input has to be
configured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input 'IN1.' The CPLD input has to be configured
to take input from the JTAG Register in order for this command to have effect on the sequence.
CPLD_VERIFY_INCR – This instruction reads out the CPLD data register for the current address and increments
the address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E 2 CMOS bits need to be erased
using the corresponding erase instruction.
FPGA Section Configuration and Testing
The following section describes the configuration and testing features of the FPGA section of the Platform Manager
device.
IEEE 1149.1-Compliant Boundary Scan Testability
The FPGA section has boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port
(TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path
that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and
loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists
of dedicated I/Os: PTDI, PTDO, PTCK and PTMS. The test access port shares its power supply with one of
the VCCIO2 banks and can operate with LVCMOS3.3 or 2.5.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
FPGA Section Configuration
The FPGA section contains a test access port that can be used for device configuration and programming.
The non-volatile memory of the FPGA section can be configured in two different modes:
In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
BSCAN registers.
In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
while reprogramming takes place.
The SRAM configuration memory can be configured in three different ways:
At power-up via internal non-volatile memory.
After a refresh command is issued via the IEEE 1149.1 port.
In IEEE 1532 mode via the IEEE 1149.1 port.
Figure 57 provides a pictorial representation of the different programming modes available in the FPGA section of
the Platform Manager. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using
IEEE 1532 protocols.