DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
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Pin Descriptions and Logic Signal Connections (Cont.)<br />
Thermal Management<br />
80<br />
<strong>Platform</strong> <strong>Manager</strong> <strong>Data</strong> <strong>Sheet</strong><br />
Ball/Pin Function 208-Ball ftBGA 128-Pin TQFP Bank Dual Function Differential<br />
VMON8 H16 81<br />
VMON9GS G15<br />
VMON9 G16 83<br />
VMON10GS F15<br />
VMON10 F16 84<br />
VMON11GS E15<br />
VMON11 E16 86<br />
VMON12GS D15<br />
VMON12 D16 88<br />
1. Primary clock inputs are single-ended.<br />
2. Ensure that SLEEPN is tied to VCC via an external pull-up when the function will not be used or the <strong>Platform</strong> <strong>Manager</strong> FPGA section will<br />
not function correctly.<br />
3. VCC and VCCAUX pins must be physically tied together for proper device operation.<br />
4. PVCCA and PVCCD pins must be physically tied together for proper device operation.<br />
5. PATDI pin is the alternate JTAG Test <strong>Data</strong> In, PTDISEL Pin = 0.<br />
6. PTDI pin is the main JTAG Test <strong>Data</strong> In, PTDISEL Pin = 1.<br />
7. This pin selects the JTAG Test <strong>Data</strong> Input pin PTDI/PATDI.<br />
8. This pin has an internal pull-up.<br />
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal<br />
characteristics of a system, <strong>Lattice</strong> specifies a maximum allowable junction temperature in all device data sheets.<br />
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not<br />
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package<br />
specific thermal values.
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