DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

sysIO Buffer Banks
The FPGA I/O section has four banks (one bank per side).
64
Platform Manager Data Sheet
Each sysIO buffer bank is capable of supporting multiple I/O standards. Each bank has its own I/O supply voltage
(V CCIO ) which allows it to be completely independent from the other banks. Figure 48 shows the sysIO banks organization
around the FPGA fabric.
Figure 48. FPGA I/O Banks
Hot Socketing
The FPGA I/Os have been carefully designed to ensure predictable behavior during power-up and power-down.
Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the
system. These capabilities make the FPGA I/Os ideal for many multiple power supply and hot-swap applications.
Sleep Mode
V CCIO3
1
1
GND Bank 3
GND
The Platform Manager FPGA section has a sleep mode that allows standby current to be reduced dramatically
during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin (see Pin Description
Table).
During Sleep mode, the FPGA logic is non-operational, register contents are not maintained, and I/Os are tristated.
Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power
supplies are in their normal operating range, eliminating the need for external switching of power supplies.
Table 20 compares the characteristics of Normal, Off and Sleep modes. Sleep mode does not shut down the
power management section of the Platform Manager. If Sleep mode is not used, ensure that the SLEEPN pin is
tied high via an external pull-up to VCC.
Bank 1
40
40
Bank 2
1 37
V CCIO2*
*V CCIO2 is restricted to either 2.5V or 3.3V operation.
V CCIO0
Bank 0
GND
42
1
V CCIO1
GND