DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
DS1036 - Platform Manager Data Sheet - Lattice Semiconductor
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FPGA Output Switching Test Conditions<br />
25<br />
<strong>Platform</strong> <strong>Manager</strong> <strong>Data</strong> <strong>Sheet</strong><br />
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,<br />
voltage, and other test conditions are shown in Table 2.<br />
Figure 12. Output Test Load, LVTTL and LVCMOS Standards<br />
DUT<br />
Table 2. Test Fixture Required Components, Non-Terminated Interfaces<br />
V T<br />
R1<br />
Test Condition R1 CL Timing Ref. VT LVTTL, LVCMOS 3.3 = 1.5V —<br />
LVCMOS 2.5 = VCCIO /2 —<br />
LVTTL and LVCMOS settings (L -> H, H -> L) � 0pF LVCMOS 1.8 = VCCIO /2 —<br />
LVCMOS 1.5 = VCCIO/2 —<br />
LVCMOS 1.2 = VCCIO /2 —<br />
LVTTL and LVCMOS 3.3 (Z -> H)<br />
LVTTL and LVCMOS 3.3 (Z -> L)<br />
1.5<br />
VOL VOH Other LVCMOS (Z -> H) VCCIO /2 VOL 188 0pF<br />
Other LVCMOS (Z -> L) VCCIO /2 VOH LVTTL + LVCMOS (H -> Z) V OH - 0.15 V OL<br />
LVTTL + LVCMOS (L -> Z) V OL - 0.15 V OH<br />
Note: Output test conditions for all other interfaces are determined by the respective standards.<br />
CL<br />
Test Poi n t
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