DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Voltage at the VMONx Pins VMON = ADC code (12 bits 1 , converted to decimal) * 2mV 1 2 Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I C/SMBUS interface Controlling Power Supply Output Voltage by Margin/Trim Block 32 Platform Manager Data Sheet One of the key features of the Platform Manager is its ability to make adjustments to the power supplies that it may also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device. The Trim and Margin Block can adjust voltages of up to eight different power supplies through TrimCells as shown in Figure 16. The DC-DC blocks in the figure represent virtually any type of DC power supply that has a trim or voltage adjustment input. This can be an off-the-shelf unit or custom circuit designed around a switching regulator IC. The interface between the Platform Manager and the DC power supply is represented by a single resistor (R1 to R8) to simplify the diagram. Each of these resistors represents a resistor network. Other control signals driving the Margin/Trim Block are: CPLD_VPS[1:0] – Voltage profile selection signals generated by the CPLD. These control signals are common to all eight TrimCells and are used to select the active voltage profile for all TrimCells together. ADC input – Used to determine the trimmed DC-DC converter voltage. CPLD_CLT_EN – Only from the CPLD, used to enable closed loop trimming of all TrimCells together. Next to each DC-DC converter, four voltages are shown. These voltages correspond to the operating voltage profile of the Margin/Trim Block. When the CPLD_VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for the normal circuit operation) The output voltage of the DC-DC converter controlled by the Trim 1 pin of the Platform Manager will be 1V and that TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim 2, Trim 3 and Trim 8 pins output 1.2V, 1.5V and 3.3V respectively. When the CPLD_VPS[1:0] = 01, representing Voltage Profile 1 being active: The DC-DC output voltage controlled by Trim 1, 2, 3, and 8 pins will be 1.05V, 1.26V, 1.57V, and 3.46V. These supply voltages correspond to 5% above their respective normal operating voltage (also called as margin high). Similarly, when CPLD_VPS[1:0] = 11, all DC-DC converters are margined low by 5%.
Figure 16. Platform Manager Trim and Margin Block Default Profile 0 Selected Digital Closed Loop and I2C Interface Control Input From ADC Mux Read – 10-bit ADC Code Platform Manager Margin/Trim Block TrimCell #1* (Closed Loop) TrimCell #2* (I 2 C Update) TrimCell #3 (I 2 C Update) TrimCell #8 (Register 0) Trim 1 Trim 2 Trim 3 Trim 8 CPLD Control Signals CPLD_CLT_EN, CPLD_VPS[0:1] 33 DC-DC Trim-in Platform Manager Data Sheet There are up to eight TrimCells in the Platform Manager device, enabling simultaneous control of up to eight individual power supplies (six in the 128-pin TQFP package option). Each TrimCell can generate up to four trimming voltages to control the output voltage of the DC-DC converter. R1** R2** R3** R8** V IN V IN V IN DC-DC Trim-in DC-DC Trim-in DC-DC Trim-in *TrimCell #1 and TrimCell #2 (Trim 1 and Trim 2) are not available in the 128-pin TQFP package option. **Indicates resistor network V IN DC-DC Output Voltage Controlled by Profiles 0 1 2 3 1V (CLT) 1.05V 0.97V 0.95V 1.2V (I 2 C) 1.26V 1.16V 1.14V 1.5V (I 2 C) 1.57V 1.45V 1.42V 3.3V (EE) 3.46V 3.20V 3.13V
Page 1 and 2: February 2012 Data Sheet DS1036 Fea
Page 3 and 4: Figure 1. Typical Platform Manager
Page 5 and 6: Recommended Operating Conditions 1,
Page 7 and 8: ESD Performance All pins Pin Group
Page 9 and 10: 1, 2, 3, 4 Programming and Erase Su
Page 11 and 12: ADC Characteristics ADC Error Budge
Page 13 and 14: sysIO Recommended Operating Conditi
Page 15 and 16: Figure 5. Differential LVPECL 15 Pl
Page 17 and 18: Timing for Power Management JTAG Op
Page 19 and 20: Typical FPGA Building Block Functio
Page 21 and 22: FPGA Section Internal Timing Parame
Page 23 and 24: Flash Download Time FPGA JTAG Port
Page 25 and 26: FPGA Output Switching Test Conditio
Page 27 and 28: AGOOD Logic Signal 27 Platform Mana
Page 29 and 30: Table 4. Trip Point Table Used For
Page 31: 31 Platform Manager Data Sheet VMON
Page 35 and 36: Figure 18. Voltage Profile Control
Page 37 and 38: 37 Platform Manager Data Sheet DAC
Page 39 and 40: CPLD Block 39 Platform Manager Data
Page 41 and 42: 41 Platform Manager Data Sheet cuit
Page 43 and 44: Figure 27. Platform Manager in I 2
Page 45 and 46: Table 11. I 2 C Control Registers 4
Page 47 and 48: Table 13. V MON Address Selection T
Page 49 and 50: Figure 33. I 2 C Output Monitor and
Page 51 and 52: 51 Platform Manager Data Sheet The
Page 53 and 54: 53 Platform Manager Data Sheet Desi
Page 55 and 56: Figure 40. PFU Diagram Slice Slice
Page 57 and 58: 57 Platform Manager Data Sheet Mode
Page 59 and 60: 59 Platform Manager Data Sheet The
Page 61 and 62: Figure 46. Group of Six Programmabl
Page 63 and 64: 63 Platform Manager Data Sheet bank
Page 65 and 66: Table 20. Characteristics of Normal
Page 67 and 68: Figure 50. Platform Manager Alterna
Page 69 and 70: Overview 69 Platform Manager Data S
Page 71 and 72: Table 22. Power Management Section
Page 73 and 74: 73 Platform Manager Data Sheet CFG_
Page 75 and 76: 75 Platform Manager Data Sheet Leav
Page 77 and 78: Pin Descriptions and Logic Signal C
Page 79 and 80: Pin Descriptions and Logic Signal C
Page 81: Part Number Description Device Fami

DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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