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DS1036 - Platform Manager Data Sheet - Lattice Semiconductor

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Figure 49. <strong>Platform</strong> <strong>Manager</strong> JTAG Interconnection Configuration Diagram<br />

APS<br />

TMS<br />

TDO<br />

TDI<br />

TCK<br />

TDISEL<br />

Board<br />

3.3V<br />

To Other Board<br />

Devices<br />

Programming <strong>Platform</strong> <strong>Manager</strong>: Alternate Method<br />

66<br />

<strong>Platform</strong> <strong>Manager</strong> <strong>Data</strong> <strong>Sheet</strong><br />

Some applications require that the <strong>Platform</strong> <strong>Manager</strong> be programmed before turning the power on to the entire circuit<br />

board. To meet such application needs, the <strong>Platform</strong> <strong>Manager</strong> provides an alternate programming method<br />

which enables the programming of the <strong>Platform</strong> <strong>Manager</strong> device through the JTAG chain with a separate power<br />

supply applied just to the programming section of the <strong>Platform</strong> <strong>Manager</strong> device with the main power supply of the<br />

board turned off.<br />

Three special purpose pins, APS, PATDI and PTDISEL, enable programming of the un-programmed <strong>Platform</strong> <strong>Manager</strong><br />

under such circumstances. The APS pin provides power to the programming circuitry of the <strong>Platform</strong> <strong>Manager</strong><br />

device (when PVCCD and PVCCA are unpowered). The PVCCJ pin must be powered to enable the JTAG port.<br />

The PATDI pin provides an alternate connection to the JTAG header while bypassing all the un-powered devices in<br />

the JTAG chain. PTDISEL pin enables switching between the PATDI and the standard JTAG signal PTDI. When the<br />

internally pulled-up PTDISEL = 1, standard PTDI pin is enabled and when the PTDISEL = 0, PATDI is enabled.<br />

In order to use this feature the JTAG signals of the <strong>Platform</strong> <strong>Manager</strong> are connected to the header as shown in<br />

Figure 50. Note: The <strong>Platform</strong> <strong>Manager</strong> should be the last device in the JTAG chain.<br />

After programming, the APS pin MUST be left floating when the PVCCD and PVCCA pins are powered.<br />

Alternate PTDI Selection Via JTAG Command<br />

FTCK<br />

Other<br />

VCC<br />

FTDO<br />

FTDI<br />

FTMS<br />

VCCIO2<br />

<strong>Platform</strong> <strong>Manager</strong><br />

When the PTDISEL pin held high and four consecutive IDCODE instructions are issued, <strong>Platform</strong> <strong>Manager</strong><br />

responds by making its active JTAG data input the PATDI pin. When PATDI is selected, data on its PTDI pin is<br />

ignored until the JTAG state machine returns to the Test-Logic-Reset state.<br />

This method of selecting PATDI takes advantage of the fact that a JTAG device with an IDCODE register will automatically<br />

load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG<br />

capability permits blind interrogation of devices so that their location in a serial chain can be identified without having<br />

to know anything about them in advance. A blind interrogation can be made using only the PTMS and PTCK<br />

control pins, which means PTDI and PTDO are not required for performing the operation. Figure 50 illustrates the<br />

logic for selecting whether the PTDI or PATDI pin is the active data input to <strong>Platform</strong> <strong>Manager</strong>.<br />

PTCK<br />

APS<br />

PTDI<br />

PVCCA/D<br />

PTDO<br />

PVCCJ<br />

PTMS<br />

PATDI<br />

PTDISEL<br />

From Other Board<br />

Devices

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