The Art of the Helicopter John Watkinson - Karatunov.net

Fig. 7.38 Producing two’s complement from real bipolar signals. At (a) an offset of half scale is added to the
input. The offset input is converted (b) to pure binary. The MSB is inverted at (c) to produce two’s complement.
The two’s complement system allows two sample values to be added, or mixed, and
the result will be referred to the system midrange; this is analogous to adding analog
signals in a synchro differential or adding pushrod movements in a mechanical mixer.
Figure 7.39 illustrates how adding two’s complement samples simulates the control
mixing process. The waveform of input A is depicted by solid black samples, and that
of B by samples with a solid outline. The result of mixing is the linear sum of the
two waveforms obtained by adding pairs of sample values. The dashed lines depict the
output values. Beneath each set of samples is the calculation that will be seen to give
the correct result. Note that the calculations are in pure binary. No special arithmetic
is needed to handle two’s complement numbers.
It is often necessary to phase reverse or invert a control signal, for example in a
cyclic/collective mixer the lateral cyclic signal needs to be added to the collective signal
on one side of the swashplate but subtracted on the other. Using inversion, signal
subtraction can be performed using only adding logic. The inverted input is added to
perform a subtraction, just as in the analog domain. This permits a significant saving
in hardware complexity, since only carry logic is necessary and no borrow mechanism
need be supported.
The process of inversion in two’s complement is simple. All bits of the sample value
are inverted to form the one’s complement, and one is added. This can be checked by
mentally inverting some of the values in Figure 7.37. The inversion is transparent and
performing a second inversion gives the original sample values. When a binary counter
is incremented it will eventually reach the all-ones condition. A further count will result
in an overflow condition. For example, if a four-bit counter is at 1111 (15 decimal) an
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