J-Link / J-Trace User Guide (UM08001) - Microcontrollers
J-Link / J-Trace User Guide (UM08001) - Microcontrollers
J-Link / J-Trace User Guide (UM08001) - Microcontrollers
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5.8.1.4 Type 3: No reset<br />
No reset is performed. Nothing happens.<br />
5.8.1.5 Type 4: Hardware, halt with WP<br />
The hardware RESET pin is used to reset the CPU. After reset release, J-<strong>Link</strong> continuously<br />
tries to halt the CPU using a watchpoint. This typically halts the CPU shortly<br />
after reset release; the CPU can in most systems execute some instructions before it<br />
is halted.<br />
The number of instructions executed depends primarily on the JTAG speed: the<br />
higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be<br />
halted before executing any instruction, because the start of the CPU is delayed after<br />
reset release<br />
5.8.1.6 Type 5: Hardware, halt with DBGRQ<br />
The hardware RESET pin is used to reset the CPU. After reset release, J-<strong>Link</strong> continuously<br />
tries to halt the CPU using the DBGRQ. This typically halts the CPU shortly after<br />
reset release; the CPU can in most systems execute some instructions before it is<br />
halted.<br />
The number of instructions executed depends primarily on the JTAG speed: the<br />
higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be<br />
halted before executing any instruction, because the start of the CPU is delayed after<br />
reset release.<br />
5.8.1.7 Type 6: Software<br />
This reset strategy is only a software reset. "Software reset" means basically no<br />
reset, just changing the CPU registers such as PC and CPSR. This reset strategy sets<br />
the CPU registers to their after-Reset values:<br />
• PC = 0<br />
• CPSR = 0xD3 (Supervisor mode, ARM, IRQ / FIQ disabled)<br />
• All SPSR registers = 0x10<br />
• All other registers (which are unpredictable after reset) are set to 0.<br />
• The hardware RESET pin is not affected.<br />
5.8.1.8 Type 7: Reserved<br />
Reserved reset type.<br />
5.8.1.9 Type 8: Software, for ATMEL AT91SAM7 MCUs<br />
The reset pin of the device is disabled by default. This means that the reset strategies<br />
which rely on the reset pin (low pulse on reset) do not work by default. For this<br />
reason a special reset strategy has been made available.<br />
It is recommended to use this reset strategy. This special reset strategy resets the<br />
peripherals by writing to the RSTC_CR register. Resetting the peripherals puts all<br />
peripherals in the defined reset state. This includes memory mapping register, which<br />
means that after reset flash is mapped to address 0. It is also possible to achieve the<br />
same effect by writing 0x4 to the RSTC_CR register located at address 0xfffffd00.<br />
5.8.1.10 Type 9: Hardware, for NXP LPC MCUs<br />
After reset a bootloader is mapped at address 0 on ARM 7 LPC devices. This reset<br />
strategy performs a reset via reset strategy Type 1 in order to reset the CPU. It also<br />
ensures that flash is mapped to address 0 by writing the MEMMAP register of the LPC.<br />
This reset strategy is the recommended one for all ARM 7 LPC devices.<br />
J-<strong>Link</strong> / J-<strong>Trace</strong> (<strong>UM08001</strong>) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG<br />
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