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J-Link / J-Trace ARM User guide of
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Revision Date By Explanation 86 100
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Revision Date By Explanation 57 081
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Revision Date By Explanation 28 070
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About this document This document d
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11 Table of Contents 1 Introduction
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5.5 Multi-core debugging ..........
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10.2.1 Rules for series terminators
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Chapter 1 Introduction This chapter
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1.2 Supported OS J-Link/J-Trace can
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1.3.1 Model comparison The followin
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LOW level input voltage (V IL ) V I
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1.3.3 J-Link Ultra J-Link Ultra is
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• Serial Wire Viewer supported
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1.3.6 J-Trace ARM J-Trace is a JTAG
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1.3.7 J-Trace for Cortex-M3 J-Trace
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1.3.8 Flasher ARM Flasher ARM is a
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1.4 Common features of the J-Link p
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1.6 Supported IDEs J-Link / J-Trace
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Chapter 2 Licensing This chapter de
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2.2 Software components requiring a
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2.3.3 Device-based license The devi
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2.4 Legal use of SEGGER J-Link soft
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2.5.3 J-Link Pro J-Link Pro is a JT
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2.6 J-Link OEM versions There are s
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2.6.6 IAR: J-Trace IAR J-Trace is a
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2.8 Illegal Clones Clones are copie
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Chapter 3 Setup This chapter descri
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2. The Welcome dialog box is opened
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3.2 Setting up the USB interface Af
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3.3 Uninstalling the J-Link USB dri
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3.4.1.2 Connecting via Ethernet onl
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3.4.2.2 Configuring J-Link via web
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3.5.2 Using the J-Link configurator
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Chapter 4 J-Link and J-Trace relate
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4.1.2 List of additional software p
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4.2.2 SWO Analyzer SWO Analyzer (SW
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4.2.4 J-Link STM32 Commander (Comma
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4.2.6 J-Mem Memory Viewer J-Mem dis
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4.2.8 J-Link RDI (Remote Debug Inte
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4.3 Dedicated flash programming uti
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4.3.5.2 Purchasing the source code
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4.5 Using the J-LinkARM.dll 4.5.1 W
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.6.3 Connecting to a J-Link / J-Tr
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5.7.1.2 Settings In the Settings se
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5.7.1.3 Break/Watch In the Break/Wa
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5.7.1.7 SWV In this section SWV inf
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5.8.1.4 Type 3: No reset No reset i
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5.8.2.6 Type 5: Reset core & periph
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5.10 J-Link script files In some si
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Prototype __api__ int JTAG_WriteIR(
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Note: All global variables are trea
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• ARM1176JFS • CORTEX_M0 • CO
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5.11 Command strings The behavior o
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Syntax map exclude - Example This i
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Syntax SetCheckModeAfterRead = 0 |
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5.11.2 Using command strings 5.11.2
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5.12 Switching off CPU clock during
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Chapter 6 Flash download and flash
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6.2 Licensing Some J-Links are avai
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- Page 175 and 176: PIN SIGNAL TYPE Description 15 RESE
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- Page 179 and 180: PIN SIGNAL Description 22 Trace sig
- Page 181 and 182: Parameter Min. Max. Explanation Tsh
- Page 183 and 184: Pins 3, 5, 15, 17, 19 are GND pins
- Page 185 and 186: Chapter 9 Background information Th
- Page 187 and 188: 9.1.4 The TAP controller The TAP co
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- Page 205 and 206: 11.2 Troubleshooting 11.2.1 General
- Page 207 and 208: 11.3 Signal analysis The following
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- Page 211 and 212: Chapter 12 Glossary This chapter de
- Page 213 and 214: ID Identifier. IEEE 1149.1 The IEEE
- Page 215 and 216: TDO The electronic signal output fr
- Page 217 and 218: Chapter 13 Literature and reference
- Page 219 and 220: A Adaptive clocking ...............
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