J-Link / J-Trace User Guide (UM08001) - Microcontrollers

9.1.4 The TAP controller
The TAP controller is a synchronous finite state machine that responds to changes at
the TMS and TCK signals of the TAP and controls the sequence of operations of the
circuitry.
TAP controller state diagram
tms=1
tms=0
9.1.4.1 State descriptions
Reset
The test logic is disabled so that normal operation of the chip logic can continue
unhindered. No matter in which state the TAP controller currently is, it can change
into Reset state if TMS is high for at least 5 clock cycles. As long as TMS is high, the
TAP controller remains in Reset state.
Idle
Idle is a TAP controller state between scan (DR or IR) operations. Once entered, this
state remains active as long as TMS is low.
DR-Scan
Temporary controller state. If TMS remains low, a scan sequence for the selected
data registers is initiated.
IR-Scan
Reset
Idle
Temporary controller state. If TMS remains low, a scan sequence for the instruction
register is initiated.
Capture-DR
Data may be loaded in parallel to the selected test data registers.
Shift-DR
tms=0
tms=1
DR-Scan
tms=1 tms=1
Capture-DR
Shift-DR
Exit1-DR
Exit1-IR
tms=1 tms=1
tms=0 tms=0
Pause-DR
tms=0 tms=0
Exit2-DR
Update-DR
tms=1 tms=1
IR-Scan
tms=0 tms=0
Capture-IR
tms=0 tms=0
Pause-IR
Update-IR
The test data register connected between TDI and TDO shifts data one stage towards
the serial output with each clock.
J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG
Shift-IR
tms=0 tms=0
tms=1 tms=1
tms=0 tms=0
tms=1 tms=1
Exit2-IR
tms=1 tms=1
tms=1 tms=0 tms=1 tms=0
187