J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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14 7.4.4 Stellaris LM3S600 Series .........................................................................161 7.4.5 Stellaris LM3S800 Series .........................................................................161 7.4.6 Stellaris LM3S2000 Series .......................................................................161 7.4.7 Stellaris LM3S6100 Series .......................................................................161 7.4.8 Stellaris LM3S6400 Series .......................................................................161 7.4.9 Stellaris LM3S6700 Series .......................................................................161 7.4.10 Stellaris LM3S6900 Series .......................................................................161 7.5 NXP......................................................................................................162 7.5.1 LPC ......................................................................................................163 7.6 OKI ......................................................................................................165 7.6.1 ML67Q40x.............................................................................................165 7.7 ST Microelectronics.................................................................................166 7.7.1 STR 71x................................................................................................167 7.7.2 STR 73x................................................................................................167 7.7.3 STR 75x................................................................................................167 7.7.4 STR91x.................................................................................................167 7.7.5 STM32 ..................................................................................................167 7.8 Texas Instruments .................................................................................169 7.8.1 TMS470 ................................................................................................169 8 Target interfaces and adapters ....................................................................................171 8.1 20-pin JTAG/SWD connector ....................................................................172 8.1.1 Pinout for JTAG ......................................................................................172 8.1.2 Pinout for SWD ......................................................................................174 8.2 38-pin Mictor JTAG and Trace connector....................................................177 8.2.1 Connecting the target board ....................................................................177 8.2.2 Pinout...................................................................................................178 8.2.3 Assignment of trace information pins between ETM architecture versions .......180 8.2.4 Trace signals .........................................................................................180 8.3 19-pin JTAG/SWD and Trace connector .....................................................182 8.3.1 Target power supply ...............................................................................183 8.4 Adapters ...............................................................................................184 9 Background information ...............................................................................................185 9.1 JTAG ....................................................................................................186 9.1.1 Test access port (TAP) ............................................................................186 9.1.2 Data registers........................................................................................186 9.1.3 Instruction register.................................................................................186 9.1.4 The TAP controller ..................................................................................187 9.2 Embedded Trace Macrocell (ETM) .............................................................189 9.2.1 Trigger condition ....................................................................................189 9.2.2 Code tracing and data tracing ..................................................................189 9.2.3 J-Trace integration example - IAR EWARM .................................................189 9.3 Embedded Trace Buffer (ETB) ..................................................................193 9.4 Flash programming ................................................................................194 9.4.1 How does flash programming via J-Link / J-Trace work? ..............................194 9.4.2 Data download to RAM............................................................................194 9.4.3 Data download via DCC...........................................................................194 9.4.4 Available options for flash programming ....................................................194 9.5 J-Link / J-Trace firmware.........................................................................196 9.5.1 Firmware update....................................................................................196 9.5.2 Invalidating the firmware ........................................................................196 10 Designing the target board for trace ..........................................................................199 10.1 Overview of high-speed board design........................................................200 10.1.1 Avoiding stubs .......................................................................................200 10.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths) ...............................200 10.1.3 Minimizing Crosstalk ...............................................................................200 10.1.4 Using impedance matching and termination ...............................................200 10.2 Terminating the trace signal ....................................................................201 J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG
10.2.1 Rules for series terminators .................................................................... 201 10.3 Signal requirements............................................................................... 202 11 Support and FAQs .....................................................................................................203 11.1 Measuring download speed ..................................................................... 204 11.1.1 Test environment .................................................................................. 204 11.2 Troubleshooting .................................................................................... 205 11.2.1 General procedure ................................................................................. 205 11.2.2 Typical problem scenarios....................................................................... 205 11.3 Signal analysis ...................................................................................... 207 11.3.1 Start sequence...................................................................................... 207 11.3.2 Troubleshooting .................................................................................... 207 11.4 Contacting support ................................................................................ 208 11.5 Frequently Asked Questions .................................................................... 209 12 Glossary.....................................................................................................................211 13 Literature and references...........................................................................................217 J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG 15
Page 1 and 2: J-Link / J-Trace ARM User guide of
Page 3 and 4: Revision Date By Explanation 86 100
Page 9 and 10: About this document This document d
Page 11 and 12: 11 Table of Contents 1 Introduction
Page 13: 5.5 Multi-core debugging ..........
Page 17 and 18: Chapter 1 Introduction This chapter
Page 19 and 20: 1.2 Supported OS J-Link/J-Trace can
Page 21 and 22: 1.3.1 Model comparison The followin
Page 23 and 24: LOW level input voltage (V IL ) V I
Page 25 and 26: 1.3.3 J-Link Ultra J-Link Ultra is
Page 27 and 28: • Serial Wire Viewer supported
Page 29 and 30: 1.3.6 J-Trace ARM J-Trace is a JTAG
Page 31 and 32: 1.3.7 J-Trace for Cortex-M3 J-Trace
Page 33 and 34: 1.3.8 Flasher ARM Flasher ARM is a
Page 35 and 36: 1.4 Common features of the J-Link p
Page 37 and 38: 1.6 Supported IDEs J-Link / J-Trace
Page 39 and 40: Chapter 2 Licensing This chapter de
Page 41 and 42: 2.2 Software components requiring a
Page 43 and 44: 2.3.3 Device-based license The devi
Page 45 and 46: 2.4 Legal use of SEGGER J-Link soft
Page 47 and 48: 2.5.3 J-Link Pro J-Link Pro is a JT
Page 49 and 50: 2.6 J-Link OEM versions There are s
Page 51 and 52: 2.6.6 IAR: J-Trace IAR J-Trace is a
Page 53 and 54: 2.8 Illegal Clones Clones are copie
Page 55 and 56: Chapter 3 Setup This chapter descri
Page 57 and 58: 2. The Welcome dialog box is opened
Page 59 and 60: 3.2 Setting up the USB interface Af
Page 61 and 62: 3.3 Uninstalling the J-Link USB dri
Page 63 and 64: 3.4.1.2 Connecting via Ethernet onl
Page 65 and 66:
3.4.2.2 Configuring J-Link via web
Page 67 and 68:
3.5.2 Using the J-Link configurator
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Chapter 4 J-Link and J-Trace relate
Page 71 and 72:
4.1.2 List of additional software p
Page 73 and 74:
4.2.2 SWO Analyzer SWO Analyzer (SW
Page 75 and 76:
4.2.4 J-Link STM32 Commander (Comma
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4.2.6 J-Mem Memory Viewer J-Mem dis
Page 79 and 80:
4.2.8 J-Link RDI (Remote Debug Inte
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4.3 Dedicated flash programming uti
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4.3.5.2 Purchasing the source code
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4.5 Using the J-LinkARM.dll 4.5.1 W
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.6.3 Connecting to a J-Link / J-Tr
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5.7.1.2 Settings In the Settings se
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5.7.1.3 Break/Watch In the Break/Wa
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5.7.1.7 SWV In this section SWV inf
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5.8.1.4 Type 3: No reset No reset i
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5.8.2.6 Type 5: Reset core & periph
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5.10 J-Link script files In some si
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Prototype __api__ int JTAG_WriteIR(
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Note: All global variables are trea
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• ARM1176JFS • CORTEX_M0 • CO
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5.11 Command strings The behavior o
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Syntax map exclude - Example This i
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Syntax SetCheckModeAfterRead = 0 |
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5.11.2 Using command strings 5.11.2
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5.12 Switching off CPU clock during
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Chapter 6 Flash download and flash
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6.2 Licensing Some J-Links are avai
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6.3 Supported devices The following
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Manufacturer Device ID Devices Free
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Manufacturer Device ID Devices NXP*
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Manufacturer Device ID Devices ST S
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6.4 Setup for different debuggers (
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Then J-Link / J-Trace has to be sel
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6.5 Setup for different debuggers (
Page 153 and 154:
Chapter 7 Device specifics This cha
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• Analog ADuC7128 • Analog ADuC
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esults. Clearly 1. is the easiest s
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7.3 Freescale J-Link has been teste
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7.4.1 Unlocking LM3Sxxx devices If
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If you experience problems with a p
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7.6 OKI J-Link has been tested with
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If you experience problems with a p
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7.8 Texas Instruments J-Link has be
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Chapter 8 Target interfaces and ada
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Pins 4, 6, 8, 10, 12, 14, 16, 18, 2
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PIN SIGNAL TYPE Description 15 RESE
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8.2 38-pin Mictor JTAG and Trace co
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PIN SIGNAL Description 22 Trace sig
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Parameter Min. Max. Explanation Tsh
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Pins 3, 5, 15, 17, 19 are GND pins
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Chapter 9 Background information Th
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9.1.4 The TAP controller The TAP co
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9.2 Embedded Trace Macrocell (ETM)
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9.2.3.2 Code coverage - Source code
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9.3 Embedded Trace Buffer (ETB) The
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9.4.4.2 JLinkArmFlash.dll - A DLL w
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Use an application (for example JLi
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Chapter 10 Designing the target boa
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10.2 Terminating the trace signal T
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Chapter 11 Support and FAQs This ch
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11.2 Troubleshooting 11.2.1 General
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11.3 Signal analysis The following
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11.5 Frequently Asked Questions Sup
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Chapter 12 Glossary This chapter de
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ID Identifier. IEEE 1149.1 The IEEE
Page 215 and 216:
TDO The electronic signal output fr
Page 217 and 218:
Chapter 13 Literature and reference
Page 219 and 220:
A Adaptive clocking ...............
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