J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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178 CHAPTER 8 Target interfaces and adapters 8.2.2 Pinout The following table lists the JTAG+Trace connector pinout. It is compatible to the "Trace Port Physical Interface" described in [ETM], 8.2.2 "Single target connector pinout". PIN SIGNAL Description 1 NC No connected. 2 NC No connected. 3 NC No connected. 4 NC No connected. 5 GND Signal ground. 6 TRACECLK Clocks trace data on rising edge or both edges. 7 DBGRQ Debug request. 8 DBGACK Debug acknowledge from the test chip, high when in debug state. 9 RESET Open-collector output from the run control to the target system reset. 10 EXTTRIG Optional external trigger signal to the Embedded trace Macrocell (ETM). Not used. Leave open on target system. 11 TDO Test data output from target JTAG port. 12 VTRef Signal level reference. It is normally fed from Vdd of the target board and must not have a series resistor. 13 RTCK Return test clock from the target JTAG port. 14 VSupply Supply voltage. It is normally fed from Vdd of the target board and must not have a series resistor. 15 TCK Test clock to the run control unit from the JTAG port. Trace signal. For more information, please refer to 16 Trace signal 12 Assignment of trace information pins between ETM architecture versions on page 180. 17 TMS Test mode select from run control to the JTAG port. Trace signal. For more information, please refer to 18 Trace signal 11 Assignment of trace information pins between ETM architecture versions on page 180. 19 TDI Test data input from run control to the JTAG port. Trace signal. For more information, please refer to 20 Trace signal 10 Assignment of trace information pins between ETM architecture versions on page 180. 21 nTRST Active-low JTAG reset Table 8.5: JTAG+Trace connector pinout J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG
PIN SIGNAL Description 22 Trace signal 9 23 Trace signal 20 24 Trace signal 8 25 Trace signal 19 26 Trace signal 7 27 Trace signal 18 28 Trace signal 6 29 Trace signal 17 30 Trace signal 5 31 Trace signal 16 32 Trace signal 4 33 Trace signal 15 34 Trace signal 3 35 Trace signal 14 36 Trace signal 2 37 Trace signal 13 38 Trace signal 1 Table 8.5: JTAG+Trace connector pinout Trace signals. For more information, please refer to Assignment of trace information pins between ETM architecture versions on page 180. J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG 179
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J-Link / J-Trace ARM User guide of
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Revision Date By Explanation 86 100
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About this document This document d
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11 Table of Contents 1 Introduction
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5.5 Multi-core debugging ..........
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10.2.1 Rules for series terminators
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Chapter 1 Introduction This chapter
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1.2 Supported OS J-Link/J-Trace can
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1.3.1 Model comparison The followin
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LOW level input voltage (V IL ) V I
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1.3.3 J-Link Ultra J-Link Ultra is
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• Serial Wire Viewer supported
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1.3.6 J-Trace ARM J-Trace is a JTAG
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1.3.7 J-Trace for Cortex-M3 J-Trace
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1.3.8 Flasher ARM Flasher ARM is a
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1.4 Common features of the J-Link p
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1.6 Supported IDEs J-Link / J-Trace
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Chapter 2 Licensing This chapter de
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2.2 Software components requiring a
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2.3.3 Device-based license The devi
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2.4 Legal use of SEGGER J-Link soft
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2.5.3 J-Link Pro J-Link Pro is a JT
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2.6 J-Link OEM versions There are s
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2.6.6 IAR: J-Trace IAR J-Trace is a
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2.8 Illegal Clones Clones are copie
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Chapter 3 Setup This chapter descri
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2. The Welcome dialog box is opened
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3.2 Setting up the USB interface Af
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3.3 Uninstalling the J-Link USB dri
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3.4.1.2 Connecting via Ethernet onl
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3.4.2.2 Configuring J-Link via web
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3.5.2 Using the J-Link configurator
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Chapter 4 J-Link and J-Trace relate
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4.1.2 List of additional software p
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4.2.2 SWO Analyzer SWO Analyzer (SW
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4.2.4 J-Link STM32 Commander (Comma
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4.2.6 J-Mem Memory Viewer J-Mem dis
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4.2.8 J-Link RDI (Remote Debug Inte
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4.3 Dedicated flash programming uti
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4.3.5.2 Purchasing the source code
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4.5 Using the J-LinkARM.dll 4.5.1 W
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.6.3 Connecting to a J-Link / J-Tr
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5.7.1.2 Settings In the Settings se
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5.7.1.3 Break/Watch In the Break/Wa
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5.7.1.7 SWV In this section SWV inf
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5.8.1.4 Type 3: No reset No reset i
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5.8.2.6 Type 5: Reset core & periph
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5.10 J-Link script files In some si
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Prototype __api__ int JTAG_WriteIR(
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Note: All global variables are trea
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• ARM1176JFS • CORTEX_M0 • CO
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5.11 Command strings The behavior o
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Page 129 and 130: Syntax SetCheckModeAfterRead = 0 |
Page 131 and 132: 5.11.2 Using command strings 5.11.2
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Page 135 and 136: Chapter 6 Flash download and flash
Page 137 and 138: 6.2 Licensing Some J-Links are avai
Page 139 and 140: 6.3 Supported devices The following
Page 141 and 142: Manufacturer Device ID Devices Free
Page 143 and 144: Manufacturer Device ID Devices NXP*
Page 145 and 146: Manufacturer Device ID Devices ST S
Page 147 and 148: 6.4 Setup for different debuggers (
Page 149 and 150: Then J-Link / J-Trace has to be sel
Page 151 and 152: 6.5 Setup for different debuggers (
Page 153 and 154: Chapter 7 Device specifics This cha
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Page 165 and 166: 7.6 OKI J-Link has been tested with
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Page 169 and 170: 7.8 Texas Instruments J-Link has be
Page 171 and 172: Chapter 8 Target interfaces and ada
Page 173 and 174: Pins 4, 6, 8, 10, 12, 14, 16, 18, 2
Page 175 and 176: PIN SIGNAL TYPE Description 15 RESE
Page 177: 8.2 38-pin Mictor JTAG and Trace co
Page 181 and 182: Parameter Min. Max. Explanation Tsh
Page 183 and 184: Pins 3, 5, 15, 17, 19 are GND pins
Page 185 and 186: Chapter 9 Background information Th
Page 187 and 188: 9.1.4 The TAP controller The TAP co
Page 189 and 190: 9.2 Embedded Trace Macrocell (ETM)
Page 191 and 192: 9.2.3.2 Code coverage - Source code
Page 193 and 194: 9.3 Embedded Trace Buffer (ETB) The
Page 195 and 196: 9.4.4.2 JLinkArmFlash.dll - A DLL w
Page 197 and 198: Use an application (for example JLi
Page 199 and 200: Chapter 10 Designing the target boa
Page 201 and 202: 10.2 Terminating the trace signal T
Page 203 and 204: Chapter 11 Support and FAQs This ch
Page 205 and 206: 11.2 Troubleshooting 11.2.1 General
Page 207 and 208: 11.3 Signal analysis The following
Page 209 and 210: 11.5 Frequently Asked Questions Sup
Page 211 and 212: Chapter 12 Glossary This chapter de
Page 213 and 214: ID Identifier. IEEE 1149.1 The IEEE
Page 215 and 216: TDO The electronic signal output fr
Page 217 and 218: Chapter 13 Literature and reference
Page 219 and 220: A Adaptive clocking ...............
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J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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