- Page 1 and 2: J-Link / J-Trace ARM User guide of
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- Page 5 and 6: Revision Date By Explanation 57 081
- Page 7 and 8: Revision Date By Explanation 28 070
- Page 9 and 10: About this document This document d
- Page 11 and 12: 11 Table of Contents 1 Introduction
- Page 13 and 14: 5.5 Multi-core debugging ..........
- Page 15 and 16: 10.2.1 Rules for series terminators
- Page 17 and 18: Chapter 1 Introduction This chapter
- Page 19 and 20: 1.2 Supported OS J-Link/J-Trace can
- Page 21 and 22: 1.3.1 Model comparison The followin
- Page 23 and 24: LOW level input voltage (V IL ) V I
- Page 25 and 26: 1.3.3 J-Link Ultra J-Link Ultra is
- Page 27 and 28: • Serial Wire Viewer supported
- Page 29 and 30: 1.3.6 J-Trace ARM J-Trace is a JTAG
- Page 31 and 32: 1.3.7 J-Trace for Cortex-M3 J-Trace
- Page 33 and 34: 1.3.8 Flasher ARM Flasher ARM is a
- Page 35 and 36: 1.4 Common features of the J-Link p
- Page 37: 1.6 Supported IDEs J-Link / J-Trace
- Page 41 and 42: 2.2 Software components requiring a
- Page 43 and 44: 2.3.3 Device-based license The devi
- Page 45 and 46: 2.4 Legal use of SEGGER J-Link soft
- Page 47 and 48: 2.5.3 J-Link Pro J-Link Pro is a JT
- Page 49 and 50: 2.6 J-Link OEM versions There are s
- Page 51 and 52: 2.6.6 IAR: J-Trace IAR J-Trace is a
- Page 53 and 54: 2.8 Illegal Clones Clones are copie
- Page 55 and 56: Chapter 3 Setup This chapter descri
- Page 57 and 58: 2. The Welcome dialog box is opened
- Page 59 and 60: 3.2 Setting up the USB interface Af
- Page 61 and 62: 3.3 Uninstalling the J-Link USB dri
- Page 63 and 64: 3.4.1.2 Connecting via Ethernet onl
- Page 65 and 66: 3.4.2.2 Configuring J-Link via web
- Page 67 and 68: 3.5.2 Using the J-Link configurator
- Page 69 and 70: Chapter 4 J-Link and J-Trace relate
- Page 71 and 72: 4.1.2 List of additional software p
- Page 73 and 74: 4.2.2 SWO Analyzer SWO Analyzer (SW
- Page 75 and 76: 4.2.4 J-Link STM32 Commander (Comma
- Page 77 and 78: 4.2.6 J-Mem Memory Viewer J-Mem dis
- Page 79 and 80: 4.2.8 J-Link RDI (Remote Debug Inte
- Page 81 and 82: 4.3 Dedicated flash programming uti
- Page 83 and 84: 4.3.5.2 Purchasing the source code
- Page 85 and 86: 4.5 Using the J-LinkARM.dll 4.5.1 W
- Page 87 and 88: Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.6.3 Connecting to a J-Link / J-Tr
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5.7.1.2 Settings In the Settings se
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5.7.1.3 Break/Watch In the Break/Wa
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5.7.1.7 SWV In this section SWV inf
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5.8.1.4 Type 3: No reset No reset i
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5.8.2.6 Type 5: Reset core & periph
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5.10 J-Link script files In some si
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Prototype __api__ int JTAG_WriteIR(
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Note: All global variables are trea
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• ARM1176JFS • CORTEX_M0 • CO
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5.11 Command strings The behavior o
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Syntax map exclude - Example This i
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Syntax SetCheckModeAfterRead = 0 |
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5.11.2 Using command strings 5.11.2
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5.12 Switching off CPU clock during
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Chapter 6 Flash download and flash
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6.2 Licensing Some J-Links are avai
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6.3 Supported devices The following
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Manufacturer Device ID Devices Free
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Manufacturer Device ID Devices NXP*
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Manufacturer Device ID Devices ST S
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6.4 Setup for different debuggers (
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Then J-Link / J-Trace has to be sel
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6.5 Setup for different debuggers (
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Chapter 7 Device specifics This cha
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• Analog ADuC7128 • Analog ADuC
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esults. Clearly 1. is the easiest s
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7.3 Freescale J-Link has been teste
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7.4.1 Unlocking LM3Sxxx devices If
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If you experience problems with a p
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7.6 OKI J-Link has been tested with
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If you experience problems with a p
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7.8 Texas Instruments J-Link has be
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Chapter 8 Target interfaces and ada
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Pins 4, 6, 8, 10, 12, 14, 16, 18, 2
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PIN SIGNAL TYPE Description 15 RESE
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8.2 38-pin Mictor JTAG and Trace co
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PIN SIGNAL Description 22 Trace sig
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Parameter Min. Max. Explanation Tsh
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Pins 3, 5, 15, 17, 19 are GND pins
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Chapter 9 Background information Th
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9.1.4 The TAP controller The TAP co
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9.2 Embedded Trace Macrocell (ETM)
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9.2.3.2 Code coverage - Source code
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9.3 Embedded Trace Buffer (ETB) The
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9.4.4.2 JLinkArmFlash.dll - A DLL w
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Use an application (for example JLi
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Chapter 10 Designing the target boa
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10.2 Terminating the trace signal T
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Chapter 11 Support and FAQs This ch
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11.2 Troubleshooting 11.2.1 General
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11.3 Signal analysis The following
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11.5 Frequently Asked Questions Sup
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Chapter 12 Glossary This chapter de
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ID Identifier. IEEE 1149.1 The IEEE
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TDO The electronic signal output fr
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Chapter 13 Literature and reference
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A Adaptive clocking ...............
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