J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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154 CHAPTER 7 Device specifics 7.1 Analog Devices J-Link has been tested with the following MCUs from Analog Devices, but should work with any ARM7/9 and Cortex-M3 device: • ADuC7020x62 • ADuC7021x32 • ADuC7021x62 • ADuC7022x32 • ADuC7022x62 • ADuC7024x62 • ADuC7025x32 • ADuC7025x62 • ADuC7026x62 • ADuC7027x62 • ADuC7030 • ADuC7031 • ADuC7032 • ADuC7033 • ADuC7060 • ADuC7128 • ADuC7129 • ADuC7229x126 If you experience problems with a particular device, do not hesitate to contact Segger. 7.1.1 ADuC7xxx All devices of this family are supported by J-Link. 7.1.1.1 Software reset A special reset strategy has been made available for Analog Devices ADuC7xxx MCUs. This special reset strategy is a software reset. "Software reset" means basically no reset, just changing the CPU registers such as PC and CPSR. The software reset for Analog Devices ADuC7xxxx executes the following sequence: • The CPU is halted • A software reset sequence is downloaded to RAM • A breakpoint at address 0 is set • The software reset sequence is executed. It is recommended to use this reset strategy. This sequence performs a reset of CPU and peripherals and halts the CPU before executing instructions of the user program. It is the recommended reset sequence for Analog Devices ADuC7xxx MCUs and works with these devices only. This information is applicable to the following devices: • Analog ADuC7020x62 • Analog ADuC7021x32 • Analog ADuC7021x62 • Analog ADuC7022x32 • Analog ADuC7022x62 • Analog ADuC7024x62 • Analog ADuC7025x32 • Analog ADuC7025x62 • Analog ADuC7026x62 • Analog ADuC7027x62 • Analog ADuC7030 • Analog ADuC7031 • Analog ADuC7032 • Analog ADuC7033 J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG
• Analog ADuC7128 • Analog ADuC7129 • Analog ADuC7229x126 J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG 155
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J-Link / J-Trace ARM User guide of
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Revision Date By Explanation 86 100
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About this document This document d
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11 Table of Contents 1 Introduction
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5.5 Multi-core debugging ..........
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10.2.1 Rules for series terminators
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Chapter 1 Introduction This chapter
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1.2 Supported OS J-Link/J-Trace can
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1.3.1 Model comparison The followin
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LOW level input voltage (V IL ) V I
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1.3.3 J-Link Ultra J-Link Ultra is
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• Serial Wire Viewer supported
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1.3.6 J-Trace ARM J-Trace is a JTAG
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1.3.7 J-Trace for Cortex-M3 J-Trace
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1.3.8 Flasher ARM Flasher ARM is a
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1.4 Common features of the J-Link p
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1.6 Supported IDEs J-Link / J-Trace
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Chapter 2 Licensing This chapter de
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2.2 Software components requiring a
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2.3.3 Device-based license The devi
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2.4 Legal use of SEGGER J-Link soft
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2.5.3 J-Link Pro J-Link Pro is a JT
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2.6 J-Link OEM versions There are s
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2.6.6 IAR: J-Trace IAR J-Trace is a
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2.8 Illegal Clones Clones are copie
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Chapter 3 Setup This chapter descri
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2. The Welcome dialog box is opened
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3.2 Setting up the USB interface Af
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3.3 Uninstalling the J-Link USB dri
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3.4.1.2 Connecting via Ethernet onl
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3.4.2.2 Configuring J-Link via web
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3.5.2 Using the J-Link configurator
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Chapter 4 J-Link and J-Trace relate
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4.1.2 List of additional software p
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4.2.2 SWO Analyzer SWO Analyzer (SW
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4.2.4 J-Link STM32 Commander (Comma
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4.2.6 J-Mem Memory Viewer J-Mem dis
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4.2.8 J-Link RDI (Remote Debug Inte
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4.3 Dedicated flash programming uti
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4.3.5.2 Purchasing the source code
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4.5 Using the J-LinkARM.dll 4.5.1 W
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
Page 103 and 104: 5.6 Connecting multiple J-Links / J
Page 105 and 106: 5.6.3 Connecting to a J-Link / J-Tr
Page 107 and 108: 5.7.1.2 Settings In the Settings se
Page 109 and 110: 5.7.1.3 Break/Watch In the Break/Wa
Page 111 and 112: 5.7.1.7 SWV In this section SWV inf
Page 113 and 114: 5.8.1.4 Type 3: No reset No reset i
Page 115 and 116: 5.8.2.6 Type 5: Reset core & periph
Page 117 and 118: 5.10 J-Link script files In some si
Page 119 and 120: Prototype __api__ int JTAG_WriteIR(
Page 121 and 122: Note: All global variables are trea
Page 123 and 124: • ARM1176JFS • CORTEX_M0 • CO
Page 125 and 126: 5.11 Command strings The behavior o
Page 127 and 128: Syntax map exclude - Example This i
Page 129 and 130: Syntax SetCheckModeAfterRead = 0 |
Page 131 and 132: 5.11.2 Using command strings 5.11.2
Page 133 and 134: 5.12 Switching off CPU clock during
Page 135 and 136: Chapter 6 Flash download and flash
Page 137 and 138: 6.2 Licensing Some J-Links are avai
Page 139 and 140: 6.3 Supported devices The following
Page 141 and 142: Manufacturer Device ID Devices Free
Page 143 and 144: Manufacturer Device ID Devices NXP*
Page 145 and 146: Manufacturer Device ID Devices ST S
Page 147 and 148: 6.4 Setup for different debuggers (
Page 149 and 150: Then J-Link / J-Trace has to be sel
Page 151 and 152: 6.5 Setup for different debuggers (
Page 153: Chapter 7 Device specifics This cha
Page 157 and 158: esults. Clearly 1. is the easiest s
Page 159 and 160: 7.3 Freescale J-Link has been teste
Page 161 and 162: 7.4.1 Unlocking LM3Sxxx devices If
Page 163 and 164: If you experience problems with a p
Page 165 and 166: 7.6 OKI J-Link has been tested with
Page 167 and 168: If you experience problems with a p
Page 169 and 170: 7.8 Texas Instruments J-Link has be
Page 171 and 172: Chapter 8 Target interfaces and ada
Page 173 and 174: Pins 4, 6, 8, 10, 12, 14, 16, 18, 2
Page 175 and 176: PIN SIGNAL TYPE Description 15 RESE
Page 177 and 178: 8.2 38-pin Mictor JTAG and Trace co
Page 179 and 180: PIN SIGNAL Description 22 Trace sig
Page 181 and 182: Parameter Min. Max. Explanation Tsh
Page 183 and 184: Pins 3, 5, 15, 17, 19 are GND pins
Page 185 and 186: Chapter 9 Background information Th
Page 187 and 188: 9.1.4 The TAP controller The TAP co
Page 189 and 190: 9.2 Embedded Trace Macrocell (ETM)
Page 191 and 192: 9.2.3.2 Code coverage - Source code
Page 193 and 194: 9.3 Embedded Trace Buffer (ETB) The
Page 195 and 196: 9.4.4.2 JLinkArmFlash.dll - A DLL w
Page 197 and 198: Use an application (for example JLi
Page 199 and 200: Chapter 10 Designing the target boa
Page 201 and 202: 10.2 Terminating the trace signal T
Page 203 and 204: Chapter 11 Support and FAQs This ch
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11.2 Troubleshooting 11.2.1 General
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11.3 Signal analysis The following
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11.5 Frequently Asked Questions Sup
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Chapter 12 Glossary This chapter de
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ID Identifier. IEEE 1149.1 The IEEE
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TDO The electronic signal output fr
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Chapter 13 Literature and reference
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A Adaptive clocking ...............
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