J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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172 CHAPTER 8 Target interfaces and adapters 8.1 20-pin JTAG/SWD connector 8.1.1 Pinout for JTAG J-Link and J-Trace have a JTAG connector compatible to ARM’s Multi-ICE. The JTAG connector is a 20 way Insulation Displacement Connector (IDC) keyed box header (2.54mm male) that mates with IDC sockets mounted on a ribbon cable. The following table lists the J-Link / J-Trace JTAG pinout. PIN SIGNAL TYPE Description 1 VTref Input 2 Not connected 3 nTRST Output 5 TDI Output 7 TMS Output 9 TCK Output 11 RTCK Input 13 TDO Input 15 RESET I/O 17 DBGRQ NC 19 5V-Supply This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor. NC This pin is not connected in J-Link. Output Table 8.1: J-Link / J-Trace pinout VTref 1 2 NC nTRST 3 4 GND TDI 5 6 GND TMS 7 8 GND TCK 9 10 GND RTCK 11 12 GND TDO 13 14 GND RESET 15 16 GND DBGRQ 17 18 GND 5V-Supply 19 20 GND JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. JTAG data input of target CPU.- It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of the target CPU. JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of the target CPU. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of the target CPU. Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. JTAG data output from target CPU. Typically connected to TDO of the target CPU. Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open. This pin can be used to supply power to the target hardware. Older J-Links may not be able to supply power on this pin. For more information about how to enable/disable the power supply, please refer to Target power supply on page 174. J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system. 8.1.1.1 Target board design We strongly advise following the recommendations given by the chip manufacturer. These recommendations are normally in line with the recommendations given in the table Pinout for JTAG on page 172. In case of doubt you should follow the recommendations given by the semiconductor manufacturer. You may take any female header following the specifications of DIN 41651. For example: Harting part-no. 09185206803 Molex part-no. 90635-1202 Tyco Electronics part-no. 2-215882-0 JTAG connector J-Link Typical target connection for JTAG 5V supply VTref nTRST TDI TMS TCK RTCK TDO RESET GND 19** 8.1.1.2 Pull-up/pull-down resistors 3* 5 7 9 11* * NTRST and RTCK may not be available on some CPUs. ** Optional to supply the target board from J-Link. 1 13 15 nTRST Target board CPU Unless otherwise specified by developer’s manual, pull-ups/pull-downs are recommended to be between 2.2 kOhms and 47 kOhms. J-Link / J-Trace (UM08001) © 2004-2010 SEGGER Microcontroller GmbH & Co. KG 19 3 5 7 9 11 13 15 20 20 1 TDI TMS TCK RTCK TDO nRST Voltage Regulator VCC GND VCC 173
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J-Link / J-Trace ARM User guide of
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Revision Date By Explanation 86 100
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About this document This document d
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11 Table of Contents 1 Introduction
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5.5 Multi-core debugging ..........
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10.2.1 Rules for series terminators
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Chapter 1 Introduction This chapter
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1.2 Supported OS J-Link/J-Trace can
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1.3.1 Model comparison The followin
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LOW level input voltage (V IL ) V I
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1.3.3 J-Link Ultra J-Link Ultra is
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• Serial Wire Viewer supported
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1.3.6 J-Trace ARM J-Trace is a JTAG
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1.3.7 J-Trace for Cortex-M3 J-Trace
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1.3.8 Flasher ARM Flasher ARM is a
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1.4 Common features of the J-Link p
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1.6 Supported IDEs J-Link / J-Trace
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Chapter 2 Licensing This chapter de
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2.2 Software components requiring a
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2.3.3 Device-based license The devi
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2.4 Legal use of SEGGER J-Link soft
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2.5.3 J-Link Pro J-Link Pro is a JT
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2.6 J-Link OEM versions There are s
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2.6.6 IAR: J-Trace IAR J-Trace is a
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2.8 Illegal Clones Clones are copie
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Chapter 3 Setup This chapter descri
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2. The Welcome dialog box is opened
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3.2 Setting up the USB interface Af
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3.3 Uninstalling the J-Link USB dri
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3.4.1.2 Connecting via Ethernet onl
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3.4.2.2 Configuring J-Link via web
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3.5.2 Using the J-Link configurator
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Chapter 4 J-Link and J-Trace relate
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4.1.2 List of additional software p
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4.2.2 SWO Analyzer SWO Analyzer (SW
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4.2.4 J-Link STM32 Commander (Comma
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4.2.6 J-Mem Memory Viewer J-Mem dis
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4.2.8 J-Link RDI (Remote Debug Inte
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4.3 Dedicated flash programming uti
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4.3.5.2 Purchasing the source code
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4.5 Using the J-LinkARM.dll 4.5.1 W
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Chapter 5 Working with J-Link and J
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5.2 Indicators J-Link uses indicato
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5.2.2 Input indicator Some newer J-
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SEGGER J-Flash configuration dialog
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5.3.3 Determining values for scan c
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5.4 SWD interface The J-Link suppor
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5.5 Multi-core debugging J-Link / J
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6. Choose Project|Options and confi
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5.6 Connecting multiple J-Links / J
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5.6.3 Connecting to a J-Link / J-Tr
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5.7.1.2 Settings In the Settings se
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5.7.1.3 Break/Watch In the Break/Wa
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5.7.1.7 SWV In this section SWV inf
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5.8.1.4 Type 3: No reset No reset i
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5.8.2.6 Type 5: Reset core & periph
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5.10 J-Link script files In some si
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Prototype __api__ int JTAG_WriteIR(
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Page 135 and 136: Chapter 6 Flash download and flash
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Page 143 and 144: Manufacturer Device ID Devices NXP*
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Page 175 and 176: PIN SIGNAL TYPE Description 15 RESE
Page 177 and 178: 8.2 38-pin Mictor JTAG and Trace co
Page 179 and 180: PIN SIGNAL Description 22 Trace sig
Page 181 and 182: Parameter Min. Max. Explanation Tsh
Page 183 and 184: Pins 3, 5, 15, 17, 19 are GND pins
Page 185 and 186: Chapter 9 Background information Th
Page 187 and 188: 9.1.4 The TAP controller The TAP co
Page 189 and 190: 9.2 Embedded Trace Macrocell (ETM)
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Page 199 and 200: Chapter 10 Designing the target boa
Page 201 and 202: 10.2 Terminating the trace signal T
Page 203 and 204: Chapter 11 Support and FAQs This ch
Page 205 and 206: 11.2 Troubleshooting 11.2.1 General
Page 207 and 208: 11.3 Signal analysis The following
Page 209 and 210: 11.5 Frequently Asked Questions Sup
Page 211 and 212: Chapter 12 Glossary This chapter de
Page 213 and 214: ID Identifier. IEEE 1149.1 The IEEE
Page 215 and 216: TDO The electronic signal output fr
Page 217 and 218: Chapter 13 Literature and reference
Page 219 and 220: A Adaptive clocking ...............
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J-Link / J-Trace User Guide (UM08001) - Microcontrollers

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