Parallel Flash Loader Megafunction User Guide (PDF) - Altera

Page 10
Functional Description
Figure 4 shows an Altera CPLD functioning as a bridge to program the NAND flash
memory device through the JTAG interface.
Figure 4. Programming NAND Flash Memory Devices With the JTAG Interface
Altera CPLD
Quartus II
Software
using JTAG
Configuration Data
PFL
Open NAND
Flash
Interface
Altera
FPGA
Altera FPGA Not Used
for Flash Programming
NAND Flash
Memory
Controlling Altera FPGA Configuration from Flash Memory
You can use the PFL logic in Altera CPLDs as a configuration controller for FPGA
configuration. The PFL logic in the CPLD determines when to start the configuration
process, read the data from the flash memory device, and configure the Altera FPGA
in PS or FPP configuration scheme.
Figure 5 shows the Altera CPLD as the configuration controller for the FPGA.
Figure 5. FPGA Configuration With Flash Memory Data
Altera CPLD
PFL
Passive Serial or
Fast Passive Parallel
Interface
Altera
FPGA
Flash
Interface
Flash
Memory (1)
Note to Figure 5:
(1) CFI flash, quad SPI flash, or NAND flash.
f
For more information about multi-device FPGA configuration in PS or FPP mode,
refer to the Configuration chapter of the respective device handbook.
You can use the PFL megafunction to either program the flash memory devices,
configure your FPGA, or both; however, to perform both functions, create separate
PFL functions if any of the following conditions apply to your design:
■
■
■
You want to use fewer LEs.
You modify the flash data infrequently.
You have JTAG or In-System Programming (ISP) access to the Altera CPLD.
May 2013 Altera Corporation Parallel Flash Loader Megafunction User Guide