Parallel Flash Loader Megafunction User Guide (PDF) - Altera

Functional Description Page 15
Figure 10 shows the implementation of page mode and option bits in the CFI flash
memory device.
Figure 10. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
End Address (1)
8 Bits
Option Bits(2)
Configuration Data (Page 2)
Configuration Data (Page 1)
Configuration Data (Page 0)
32 Bits
Page 2 Address + Page-Valid
Page 1 Address + Page-Valid
Page 0 Address + Page-Valid
Notes to Figure 10:
0x000000
(1) The end address depends on the density of the flash memory device. For the address range for devices with
different densities, refer to Table 5.
(2) You must specify the byte address for the option bits sector.
Figure 11 shows the storage of the start address and Page-Valid bit for each page in
the option bits sector.
Figure 11. Page Start Address, End Address, and Page-Valid Bit Stored as Option Bits
Bit 7...Bit 1 Bit 0
0x002000 (1)
Page Start Address [19:13]
Page-Valid
Bit 7...Bit 0
0x002001
Page Start Address [27:20]
Bit 7...Bit 1
0x002002
Page End Address [19:13]
Bit 7...Bit 0
0x002003
Page End Address [27:20]
Note to Figure 11:
(1) For flash byte addressing mode.
Bits 0 to 12 for the page start address are set to zero and are not stored as option bits.
The Page-Valid bits indicate whether each page is successfully programmed. The PFL
megafunction programs the Page-Valid bits after successfully programming the
pages.
Parallel Flash Loader Megafunction User Guide
May 2013
Altera Corporation