Parallel Flash Loader Megafunction User Guide (PDF) - Altera

Functional Description Page 13
In Figure 9, address bit numbers in the PFL megafunction and the flash memory
device are the same.
Figure 9. Spansion and Micron M28, M29 Flash Memory in 16-Bit Mode
PFL
address: 23 bits
22
21
20
-
-
-
2
1
0
Flash Memory
address: 23 bits
22
21
20
-
-
-
2
1
0
Implementing Page in the Flash .pof
The PFL megafunction stores configuration data in a maximum of eight pages in a
flash memory block. Each page holds the configuration data for a single FPGA chain.
A single FPGA chain can contain more than one FPGA. For an FPGA chain with
multiple FPGAs, the PFL megafunction stores multiple SRAM Object Files (.sof) in the
same page.
The total number of pages and the size of each page depends on the density of the
flash. These pages allow you to store designs for different FPGA chains or different
designs for the same FPGA chain in different pages.
Use the generated .sof files to create a flash memory device .pof. When converting
these .sof files to a .pof, use the following address modes to determine the page
address:
■
■
■
Block mode—Allows you to specify the start and end addresses for the page.
Start mode—Allows you to specify only the start address. You can locate the start
address for each page on an 8-KB boundary. If the first valid start address is
0×000000, the next valid start address is an increment of 0×2000.
Auto mode—Allows the Quartus II software to automatically determine the start
address of the page. The Quartus II software aligns the pages on a 128-KB
boundary; for example, if the first valid start address is 0×000000, the next valid
start address is an increment of 0×20000.
1 If you are programming NAND flash, you must specify the NAND flash memory
device reserved block start address and the start address to ensure the files reside
within a 128-KB boundary.
Parallel Flash Loader Megafunction User Guide
May 2013
Altera Corporation