Parallel Flash Loader Megafunction User Guide (PDF) - Altera

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Functional Description
Table 5 lists the byte address range for CFI flash memory devices with different
densities.
Table 5. Byte Address Range
CFI Device (Megabit)
Address Range
8 0×0000000–0×00FFFFF
16 0×0000000–0×01FFFFF
32 0×0000000–0×03FFFFF
64 0×0000000–0×07FFFFF
128 0×0000000–0×0FFFFFF
256 0×0000000–0×1FFFFFF
512 0×0000000–0×3FFFFFF
1024 0×0000000–0×7FFFFFF
Using Enhanced Bitstream Compression and Decompression
The enhanced bitstream compression and decompression feature in the PFL
megafunction reduces the size of the configuration file in the flash memory device.
On average, you can reduce the file size by as much as 50% depending on the designs.
When you turn on the enhanced bitstream compression feature, the PFL
megafunction disables data encryption.
Table 6 lists the preliminary compressed data size reduction and the configuration
time comparison between typical, enhanced, and double bitstream compression
results.
Table 6. Comparison Between Typical, Enhanced, and Double Compression
FPGA Configuration
Typical Bitstream
Compression Feature
Enhanced Bitstream
Compression Feature
Double Compression
Technique
FPGA on-chip bitstream
decompression enabled
Yes No Yes
PFL enhanced bitstream
decompression enabled
No Yes Yes
Typical configuration file size
reduction
35%–55% 45%–75% 40%–60%
PS configuration time Moderate (1) Slow Moderate (1)
FPP configuration time Fast (2) Very fast (3) Not supported
Notes to Table 6:
(1) The FPGA receives compressed bitstream which decreases the duration to transmit the bitstream to the FPGA.
(2) For FPP with on-chip bitstream decompression enabled, the DCLK frequency is ×2, ×4, or ×8 the data rate, depending on the device. You can
check the relationship of the DCLK and data rate in the FPP Configuration section in the configuration chapter of the respective device handbook.
(3) For FPP with enhanced bitstream decompression enabled, the DCLK frequency is ×1 the data rate.
1 When using the PFL with compression, set the device MSEL pins set for compression or
decompression. When generating or converting a programming file, you can enable
compression. In the first few bytes during the generation of the programming file
(with compression enabled), a bit set notifies the PFL that the incoming files is a
compressed file. The ×4 DCLK-to-data are handled automatically in the PFL.
May 2013 Altera Corporation Parallel Flash Loader Megafunction User Guide