Parallel Flash Loader Megafunction User Guide (PDF) - Altera

Using the PFL Megafunction Page 31
Figure 19 shows the simulation when the FPGA configuration starts.
Figure 19. Simulation When FPGA Configuration Starts
The FPGA configuration continues until the fpga_conf_done signal is asserted high,
which indicates the configuration is complete. After the configuration process
completes, the PFL megafunction pulls the flash_nce and flash_noe signals high and
the pfl_flash_access_request signal low to indicate the configuration data is no
longer being read from the flash memory device.
Programming Altera CPLDs and Flash Memory Devices
Using the Quartus II Programmer, you can program Altera CPLDs and flash memory
device in a single step or separate steps.
To program both in a single step, first program the CPLD, then the flash memory
device. Follow these steps:
1. Open the Quartus II Programmer window and click Add File to add the .pof for
the CPLD.
2. Right-click the CPLD .pof and click Attach Flash Device.
3. In the Flash Device menu, select the density of the flash memory device to be
programmed.
4. Right-click the necessary flash memory device density and click Change File.
5. Select the .pof generated for the flash memory device. The .pof for the flash
memory device is attached to the .pof of the CPLD.
6. Add other programming files if your chain has other devices.
7. Check all the boxes in the Program/Configure column for the new .pof and click
Start to program the CPLD and flash memory device.
Parallel Flash Loader Megafunction User Guide
May 2013
Altera Corporation