Parallel Flash Loader Megafunction User Guide (PDF) - Altera

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Page 6 Functional Description Table 3 lists the types of NAND flash memory devices that the PFL megafunction supports. Table 3. Types of Supported NAND Flash Memory Device Manufacturer Device Name Density (Megabit) Micron(NAND) Micron Micron(MT29) 512 Samsung K9F1208R0C Hynix HY27US0812(1/2)B Toshiba TC58DVG02A1 1000 The PFL megafunction allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP) mode. The PFL megafunction supports configuration with FPGA on-chip data compression and data encryption. When you use compressed or encrypted configuration data for FPP configuration, the PFL megafunction holds one data byte for four DCLK cycles to ensure the DCLK frequency runs at ×4 data rate. The PFL megafunction checks if the compression or encryption feature is turned on in the configuration image before configuring in FPP mode. Hence, no additional setting is required in the PFL megafunction to specify whether the configuration file stored in the flash memory device is a compressed or uncompressed image. 1 When you turn on the enhanced bitstream compression feature, data encryption is disabled. You can program the Altera CPLDs and flash memory device in Programmer Object File (.pof), Jam Standard Test and Programming Language (STAPL) Format File (.jam), or JAM Byte Code File (.jbc) file format. The PFL megafunction does not support Raw Binary File (.rbf) format. Logic element (LE) usage varies with different PFL megafunction and Quartus II software settings. To determine the exact LE usage number, compile a PFL design with your settings using the Quartus II software. Functional Description The PFL megafunction allows you to program flash memory devices with Altera CPLDs through the JTAG interface and provides the logic to control configuration from the flash memory device to the Altera FPGA. Programming Flash Memory You can use the PFL megafunction to program the following flash memory devices with JTAG interface: ■ ■ ■ Programming CFI Flash Programming Quad SPI Flash Programming NAND Flash May 2013 Altera Corporation Parallel Flash Loader Megafunction User Guide
Functional Description Page 7 Programming CFI Flash Altera configuration devices support programming through the JTAG interface to allow in-system programming and updates. However, standard flash memory devices do not support the JTAG interface. You can use the JTAG interface in Altera CPLDs to indirectly program the flash memory device. The Altera CPLD JTAG block interfaces directly with the logic array in a special JTAG mode. This mode brings the JTAG chain through the logic array instead of the Altera CPLD boundary-scan cells (BSCs). The PFL megafunction provides JTAG interface logic to convert the JTAG stream provided by the Quartus II software and to program the CFI flash memory devices connected to the CPLD I/O pins. Figure 1 shows an Altera CPLD configured as a bridge to program the CFI flash memory device through the JTAG interface. Figure 1. Programming the CFI Flash Memory With the JTAG Interface Altera CPLD Quartus II Software using JTAG Configuration Data PFL Common Flash Interface Altera FPGA Altera FPGA Not Used for Flash Programming CFI Flash Memory The PFL megafunction supports dual P30 or P33 CFI flash memory devices in burst read mode to achieve faster configuration time. Two identical P30 or P33 CFI flash memory devices connect to the CPLD in parallel using the same data bus, clock, and control signals (Figure 2). During FPGA configuration, the FPGA DCLK frequency is four times faster than the flash_clk frequency. Figure 2. PFL Megafunction With Dual P30 or P33 CFI Flash Memory Devices P30/P33 CFI Flash Altera CPLD V CC V CC V CC 10kΩ 10kΩ 10kΩ Altera FPGA ADDR[24..0] NCE NWE NOE DATA[16..0] P30/P33 CFI Flash ADDR[24..0] NCE NWE NOE DATA[16..0] 16 16 flash_addr[24..0] flash_nce flash_nwe flash_noe flash_data[31..0] fpga_conf_done fpga_nstatus fpga_nconfig fpga_data fpga_dclk CONF_DONE nSTATUS nCONFIG DATA DCLK nCE Parallel Flash Loader Megafunction User Guide May 2013 Altera Corporation
Page 1 and 2: Parallel Flash Loader Megafunction
Page 3 and 4: Device Support Page 3 Table 1. Flas
Page 5: Device Support Page 5 Table 2 lists
Page 9 and 10: Functional Description Page 9 Figur
Page 11 and 12: Functional Description Page 11 ■
Page 13 and 14: Functional Description Page 13 In F
Page 15 and 16: Functional Description Page 15 Figu
Page 17 and 18: Functional Description Page 17 For
Page 19 and 20: Functional Description Page 19 Figu
Page 21 and 22: Using the PFL Megafunction Page 21
Page 35 and 36: PFL Megafunction In Embedded System
Page 37 and 38: PFL Megafunction In Embedded System
Page 39 and 40: Parameters Page 39 Table 13. PFL Me
Page 41 and 42: Parameters Page 41 Table 13. PFL Me
Page 43 and 44: Signals Page 43 Signals This sectio
Page 45 and 46: Signals Page 45 Table 14. PFL Signa
Page 47 and 48: Specifications Page 47 Table 15. FP
Page 49 and 50: Specifications Page 49 Use the foll
Page 51 and 52: Document Revision History Page 51

Parallel Flash Loader Megafunction User Guide (PDF) - Altera

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