The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
As can be seen, Sol's internal memory consists of four contiguous
1024-byte pages. There are two pages (C0 and C4, hexadecimal
or hex) of ROM, with Page C0 at hex addresses C000 through C3FF and
Page C4 at hex addresses C400 through C7FF. System RAM (Page C8) is
at hex addresses C800 through CBFF, and Display RAM (Page CC) is at
hex addresses CC00 through CFFF.
The six high order bits of the address are decoded in the
Address Page and I/O Port Decoder to supply the required four memory
page selection signals. The I/O Port Decoder portion of this circuit
decodes the eight high order address bits to provide outputs
that control Data Input Multiplexer switching, Data Bus Driver enablement
and I/O port selection.
The video display section consists of the Video Display Generator
and Display RAM. The RAM is a two-port memory, with the CPU
having the higher priority. Screen refresh circuitry in the Video
Display Generator controls the second port to call up data as needed
for conversion by a character generator ROM into video output signals.
Other circuitry generates horizontal and vertical sync and blanking
signals as well as cursor and video polarity options.
A 1200 Hz signal, extracted from dot clock by a divider in
the Video Display Generator, drives the Baud Rate Generator. This
generator supplies the receive and transmit clocks for the serial
data interface (SDI/UART) and provides ail frequencies required for
Baud rates between 75 and 9600. It also supplies clock signals to
the Cassette Data Interface (GDI).
A UART controls data flow through the Serial Data Interface
(SDI/UART) and provides for compatibility between the Sol and a data
communications system, be it RS-232 standard or a 20 ma current loop
device. In the transmit mode, parallel data on the Bidirectional
Data Bus is converted into serial form for transmission. Received
serial data is converted in the receive mode into parallel form for
entry into the CPU on the Internal Data Bus. SDI/UART status is also
reported to the CPU on the Internal Data Bus. The SDI/UART channel
is enabled by the port strobe from the Address Page and I/O Port
Decoder.
Circuitry within the GDI derives timing signals from clocks
supplied by the Baud Rate Generator. The Cassette Data UART functions
to 1) convert parallel data on the Bidirectional Data Bus into
serial audio signals for recording on cassette tape, and 2) convert
serial audio signals from a cassette recorder into parallel data for
entry into the CPU from the Internal Data Bus. Note that Cassette
Data UART status is also reported to the CPU on the Internal Data
Bus. Again, a UART performs the necessary parallel-to-serial and
serial-to-parallel conversions. Other GDI circuitry performs the
needed digital-to-audio and audio-to-digital conversions and provides
the signals that allow motor control for two recorders. As with the
SDI/UART, the Cassette Data UART is enabled by a port strobe from the
Address Page and I/O Port Decoder.
VIII-4